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AK8186B draft - e - 02 sep - 2012 - 1 - f eatures low phase noise pll : rms jitter < 300fs on - chip vco tunes from 1.75g hz to 2.25g hz external vco/vcxo to 5 00 mhz optional 1 differential or 2 single - ended inputs reference switch over/ holdover modes lock detect 3 pairs of 1g hz lvpecl outputs 2 pairs of 800mhz lvds outputs 8 250 mhz cmos outputs (two per lvds) serial control register interface 3.3v+/ - 5% operating voltage 2.5v - 3.3v lvpecl drive voltage operating temperature: - 40 to + 85 c package: 64 - pin leadless qfn (pb free) pin compatible with ad9516 - 3 d escription the AK8186B is a multi - output cloc k generator with sub - ps jitter performance. the on - chip vco tunes from 1.75g hz to 2.25g hz. the distribution section has three pairs of lvpecl buffers (6 outputs) and two pairs of lvds buffers (4 outputs)/eight cmos buffers (two per lvds outputs ) . the lvpecl outputs operate up to 1g hz, the lvds outputs operate up to 8 00mhz and t h e cmos outputs operate up to 250 mhz. each pair of the outpu ts has a divider. the lvpecl outputs have the division range of 1 to 32. the lvds and cmos outputs have the 1 to 1024. the AK8186B operates at 3.3v and the lvpecl outputs are supplied independently from 2.375v to 3.6v. the operating temperature range is f rom - 40 to +85 c. the part is a vailable in a 9mm 9 mm 64 - pin leadless - qfn (pb free) package. o rder ing i nformation part number marking shipping packaging package temperature range AK8186B AK8186B tape and reel 64 - pin l eadless qfn - 4 0 to 85 multi out put cl ock generator with integrated 2.0 ghz vco AK8186B p r e l i m i n a r y
AK8186B sep - 2012 draft - e - 02 - 2 - b lock d iagram figure 1 . AK8186B block diagram cp rset cs s clk sdio sdo out0 out 0 out1 out 1 out2 ou t2 out4 out4 out6 out 6 out3 out 3 out5 out 5 pd sync reset bypass status out7 out 7 refmon out8 out8 out9 out9 lvpecl lv ds/ cmos v co lf ld rset cp distribution reference ref_sel refin/ref1 refin /ref2 referen ce switchover status status divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 p,p+1 prescaler r divider lock detect hold a/b counter vco status ref1 ref2 n divide r phase frequency detector pll reference charge pump ldo digital logic serial control port v co divider divider 0 divider 1 divider 2 divider 3.1 divider 3. 2 divider 4 .1 divider 4 .2 divide by 2 to 6 clk clk
AK8186B draft - e - 02 sep - 2012 - 3 - table of contents features ................................ ................................ ..... - 1 - description ................................ ................................ - 1 - ordering information ................................ ............ - 1 - block diagram ................................ .......................... - 2 - pin description ................................ ......................... - 4 - pin configuration ................................ ................... - 4 - pin function ................................ ............................. - 5 - absolute maximum rat in g ................................ ..... - 7 - recommended operatin g conditions ................... - 7 - electrical character istics ................................ ...... - 7 - p ower d issipation ................................ ......................... - 7 - pll c haracteristics ................................ ....................... - 8 - c lock i nput c haracteristics ................................ ........... - 9 - c lock o utput c haracteristics ................................ ...... - 10 - t iming c haracteristics ................................ ................. - 11 - c lock o utput a dditive p hase n oise (d istribution o nly ; vco d ivider n ot u sed ) ................................ ........................ - 12 - c lock o utput p hase n oise (i nternal vco u sed ) ............ - 13 - c lock o utput a bsolute t ime j i tter (c lock g eneration u sing i nternal vco) ................................ ............................. - 14 - c lock o utput a bsolute t ime j itter (c lock g eneration u sing e xternal vcxo) ................................ .......................... - 14 - c lock o utput a dditive t ime j itter (vco d ivider n ot u sed ) .. - 15 - c lock o utput a dditive t ime j itter (vco d ivider u sed ) ... - 15 - s erial c ontrol p ort ................................ .................... - 16 - , and ................................ ................. - 17 - ld, status and refmon ................................ ........... - 17 - timing diagrams ................................ .................... - 18 - theory of operation ................................ ............. - 19 - operational configurations ............................. - 19 - internal vco and clock distribution .................... - 19 - external vco and clock distribution .................... - 20 - pll ................................ ................................ ............. - 21 - reference input ................................ ............... - 21 - reference switchover ................................ .... - 22 - r divider (reference di vider) ......................... - 22 - phase frequency detector (pfd) .................. - 23 - charge pump (cp) ................................ ............. - 23 - on - chip vco ................................ ........................ - 23 - external vco/vcxo ................................ ............. - 24 - pll external loop filter ................................ . - 24 - figure 12 example of external loop filter for the internal vco figure 13 example of external loop filter for an external vco ............................ - 24 - feedback divider (n divider) .......................... - 24 - lock detect ................................ ....................... - 26 - holdover ................................ ........................... - 28 - frequency status monitors ................................ .. - 30 - clock distribution ................................ ................ - 31 - vco divider ................................ ........................ - 31 - channel dividers for lv pecl outputs ................ - 31 - channel dividers for lvds/cmos outputs ........ - 31 - synchronizing the outputs: sync function ....... - 32 - phase offset ................................ ......................... - 32 - lvpecl outputs : out0 to out5 ....................... - 34 - lvds/cmos outputs : out6 t o out9 ............... - 34 - reset ................................ ................................ ......... - 35 - power - on reset (por) ................................ .......... - 35 - asynchronous reset by pin ...................... - 35 - soft reset by 0x00[5] ................................ ............ - 35 - power down modes ................................ .............. - 36 - chip power down by pdn pin ............................... - 36 - pll power down ................................ .................. - 36 - ref1, ref2 power down ................................ ...... - 36 - vco and clk input power down .......................... - 36 - distribution power down ................................ ..... - 36 - individual clock output power do wn (out0 to out9) - 37 - serial control port ................................ .............. - 38 - serial control port pin descriptions ......... - 38 - general description of serial control port - 38 - communication cycle ................................ .......... - 38 - the instruction word (16 bits) ............................. - 39 - write ................................ ................................ .. - 39 - read ................................ ................................ .... - 40 - bus stalling in read/write a ccess ............... - 40 - msb/lsb first transfers ................................ .. - 41 - register map ................................ ........................... - 43 - reg ister map function descriptions ................. - 46 - serial port configuration ................................ ..... - 46 - pll configuration ................................ ................. - 47 - lvpecl outputs ................................ ................... - 56 - lvds/cmos outputs ................................ ............ - 58 - lvpecl channel dividers ................................ ...... - 60 - lvds/cmos channel dividers .............................. - 62 - vco divider and clk input ................................ ... - 64 - system ................................ ................................ . - 65 - update all registers ................................ ............ - 65 - package information ................................ ........... - 66 - m echanical data ................................ ......................... - 66 - m arking ................................ ................................ ..... - 66 -
AK8186B sep - 2012 draft - e - 02 - 4 - pin d escription pin configuration figure 2 . pin configuration top view 48 out6 /out6a 47 out6 /out6b 46 out7 /out7a 45 287 /out7b 44 gnd 43 out2 42 287 41 vdd_lvpecl 40 out3 39 out3 38 vdd 37 gnd 36 out9 /out9b 35 out9 /out9a 34 287 /out8b 33 out8 /out8a vdd 1 refmon 2 ld 3 vcp 4 cp 5 status 6 re f_sel 7 8 lf 9 bypass 10 vdd 11 vdd 12 clk 13 &/. 14 nc 15 sc lk 16 64 refin /ref1 63 refin /ref2 62 cprset 61 vdd 60 vdd 59 gnd 58 rset 57 vdd 56 out0 55 287 54 vdd_lvpecl 53 out1 52 out1 51 vdd 50 v dd 49 vdd cs reset 23 3' 24 out4 25 287 26 vdd_lvpecl 27 out5 28 287 29 vdd 30 vdd 31 vdd 32
AK8186B draft - e - 02 sep - 2012 - 5 - pin function pin no. pin name pin type description 1 vdd pwr 3.3v power supply . 2 refmon out reference monitor . 3 ld out lock detect . 4 vcp --- 3.3v power supply for charge pump (cp) 5 cp out charge pump out put. connect to external loop fi lter. 6 s t atus out sta t us indication . 7 re f_sel in reference select. l: ref1 h : ref2. pulled down with 30k ? internal resistor . 8, s ync in manual sync h roni z ation and manual holdover. active low. pulled up with 30 k ? internal resistor . 9 lf in loop filter input. 10 bypass --- this pin is for bypassing the ldo to ground. 11 vdd pwr 3.3v p ower supply . 12 vdd pwr 3.3v power supply. 13 clk --- differential input for the external vco/vcxo 14 clk --- differential input for the external vco/vcxo 15 nc -- no connect. leave open or con nected to gnd. 16 sclk in serial clock for the serial control port. pulled down with 30k ? internal resistor . 17 cs in chip select for the serial control port. active low. pulled up to vdd with 30 k ? internal resistor . 1 8 nc --- no connect. leave o pen or connected to gnd. 1 9 nc --- no connect. leave open or connected to gnd. 20 nc -- no connect. leave open or connected to gnd. 21 sdo out unidirectional serial data out for serial control port . 22 sdio in/out bidirectional serial data in/out f or serial control port . 23 reset in reset. active low. pulled up with 30 k ? internal resistor . 24 pd in power down. active low. pulled up with 30 k ? internal resistor . 25 out4 out lvpecl output 4 26 out4 out lvpecl output 4 27 vdd _lvpecl pwr 2.5v to 3.3v pow er supply for lvpecl output (out4/ out4 , out5/ out5 ) . 28 out5 out lvpecl output 5 29 out5 out lvpecl output 5 30 vdd pwr 3.3v power supply 31 vdd pwr 3.3v power supply. 32 vdd pwr 3.3v power supply for out8/ out8 and out9 / out9 . (continued on next page)
AK8186B sep - 2012 draft - e - 02 - 6 - pin no. pin name pin type description 33 out8/out8a out lvds/cmos output 8 34 out8 /out8b out lvds/cmos output 8 35 out9/out9a out lvds/cmos output 9 36 out9 /out9b out lvds/cmos output 9 37 gnd pwr ground. include s external pad (epad). 38 vdd pwr 3.3v power supply . 39 out3 out lvpecl output 3 40 out3 out lvpecl output 3 41 vdd _lvpecl pwr 2.5v to 3.3v power supply for lvpecl output (out2/ out2 , out3/ out3 ). 42 out2 out lvpecl output 2 43 out2 out l vpecl output 2 44 gnd pwr ground. includes external pad (epad). 45 out7 /out7b out lvds/cmos output 7 46 out7 / out7a out lvds/cmos output 7 47 out6 /out6b out lvds/cmos output 6 48 out6 /out6a out lvds/cmos output 6 49 vdd pwr 3.3v power supp ly for out6/ out6 and out7/ out7 . 50 vdd pwr 3.3v power supply. 51 vdd pwr 3.3v power supply. 52 out1 out lvpecl output 1 53 out1 out lvpecl output 1 54 vdd _lvpecl pwr 2.5v to 3.3v power supp ly for lvpecl output (out0/ out0 , out1/ out1 ). 55 out0 out lvpecl output 0 56 out0 out lvpecl output 0 57 vdd pwr 3.3v power supply. 58 rset --- internal bias current control. nominal value = 4.12k ? 59 gnd pwr ground. 60 vdd pwr 3.3v power supply. 61 vdd pwr 3.3v power supply. 62 cprse t --- charge pump current control. nominal value = 5.1 k ? 63 refin /ref2 in differential input for the pll reference. alternatively single - ended input for ref2. 64 refin /ref1 in differential input for the pll reference. alternatively single - ended i nput for ref1. epad gnd pwr ground . the epad is connected with other gnd pins.
AK8186B draft - e - 02 sep - 2012 - 7 - a bsolute m aximum r ating table 1 over operating free - air temperature range unless otherwise noted (1) item s symbol min max unit s upply v oltage (vdd,vdd_lvpecl,vcp) vdd - 0.3 4.3 v input voltage vin gnd - 0.3 vdd+0.3 v input current iin - 10 10 ma storage temperature tstg - 55 125 ? stress beyond those listed under absolute m ax imum r atings may cause perma n ent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute - maximum - rating conditions fo r extended periods may affect device reliability. electrical par ameters are guaranteed only over the recommended operating temperature range. this device is manufactured on a cmos process, therefore, generically susceptible to damage by excessive stati c voltage. failure to observe proper handling and in stallation procedures can cause damage . akm recommends that this device is handled with appropriate precautions. r ecommended o perating c onditions table 2 parameter s ymbol co nditions m in typ m ax unit operating t emperature ta - 4 0 85 ? c supply voltage (1) vdd , vcp 3.135 3.3 3.465 v vdd_lvpecl 2.375 vdd v r set pin resistor rr connect to gnd. 4.08 4.12 4.16 k ? cprset pin resistor rc connect to gnd. 4.3 5.1 6.2 k ? b ypass pin capacitor c bp connect to vcognd. 220 n f (1) power of 2.5v or 3.3v require s to be supplied from a single source. a decoupling capacitor of 0.1 ? f for power supply line should be locat ed close to each vdd pin. electrical char a cteristics power dissipation table 3 parameter s ymbol conditions m in typ m ax unit power on default pd1 *1 0.4 0.52 w full operation pd2 *2 1. 6 2.0 w full operation pd3 *3 1. 4 1. 7 w power down pd4 0. 4 mw (*1) no clock input. default register values. not include power dissipation in external resistor s. (*2) ref1/ref2=246.575 mhz, rdiv=1 6, ndiv=14 6 , vco=2. 25ghz, vco div=2, l vpecl=562.5mhz, cm os(10pf load)=225 mhz. not include power dissipation in external resistor s. (*3 ) ref1/ref2=246.575mhz, rdiv=16, ndiv=146, vco=2.25ghz, vco div=2, lvpecl=562.5mhz, lvds=225mhz. not include power dissipation in external resistors. esd sensitive device
AK8186B sep - 2012 draft - e - 02 - 8 - pll characteristics table 4 . al l specifications at vdd= 3.3v ? 5%, vdd_lvpecl = 2 .3 75 v to vdd , ta: - 40 to +85 , unless otherwise noted parameter conditions m in typ m ax unit on chip vco frequency range 1750 225 0 mhz vco gain fvco= 2.25g hz fvco=1.97 ghz fvco= 1.75g hz 18 16 1 4 67 52 41 146 128 114 mhz/v tuning voltage 1.0 2. 5 v frequency pushing open loop - 5 5 mhz/v phase noise@100khz offset phase noise@1mhz oddset fvco=2.00g hz fvco=2.00g hz - 105 - 13 0 dbc/hz dbc/hz reference inputs (differentia l mode) input frequency refin, re f inn below 1 mhz should be dc - coupled 0 250 mhz input duty 40 60 % input sensitivity(ac - couple) 200 mvpp input slew rate 0.2 v/ns self - bias voltage,refin self - bias voltage,refinn 1.35 1.3 1.6 1.5 1.75 1. 7 v v input resistance,refin input resistance,refinn 3.3 3.7 4.8 5.3 6.2 6.9 k ? ? reference inputs (single - ended mode) input frequency(ac - couple) input frequency(dc - couple) input sensitivity(ac - couple) ref1, ref2 20 0 0.6 250 250 mhz mhz vp p input duty at vdd/2 40 60 % input slew rate 0.2 v/ns input logic high input logic low 2.0 0.8 v v input logic current - 100 +100 ? phase frequency detector pfd input frequency 100 mhz antibacklash pulse width 1.4 ns charge pump icp sink/source high value low value programmable cprset=5.1 k icp leakage cp = 0.5 to vcp - 0 .5v - 1 +1 sink/sou rce matching *1 cp = 0.5 to vcp - 0.5v - 10 2.2 +10 % icp vs vcp *2 cp = 0.5 to vcp - 0.5v - 8 3.6 + 8 % icp vs temperature cp = 0.5*v cp - 5 +5 %
AK8186B draft - e - 02 sep - 2012 - 9 - parameter conditions m in typ m ax unit prescaler (part of n divider) prescaler i n put frequency p = 1 fd p = 2 fd p = 3 fd p = 2 dm (2/3) p = 4 dm (4/5) p = 8 dm (8/9) p = 16 dm (16/17) p = 32 dm (32/33) prescaler output frequency 1e1[1]=0 1e1[1]=0 1e1[1]=0 1e1[1]=0 1e1[1]=0 1e1[1]=0 or 1 1e1[1]=0 or 1 1e1[1]=0 or 1 a,b counter input. 300 5 00 500 500 500 2250 2250 2250 300 mhz mhz mhz mhz mhz mhz mhz mhz mhz n o ise characteristics in - band phase noise of the charge pump/phase frequency detecter pll figure of merit (fom) @500 khz pfd frequency @1mhz pfd frequency @10mhz pfd frequency @50mhz p fd frequency fom = phase noise - 10log(f pfd ) - 20log(n div ) + 20log(odiv) ; where n div = n divider ratio , odiv = vco divider ratio * channel divider ratio. - 169 - 166 - 155 - 147 - 226 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz pll digital lock detect w indow required to lock to unlock after lock (hysteresis) 0x18[4] = 1 0x18[4] = 0 0x18[4] = 1 0x18[4] = 0 3.5 7.5 7 15 ns ns ns ns *1) [(|isink| - |isource|)/{(|isink|+|isource|)/2}] * 100 [%] *2) (|i1 - i2|)/(|i1+i2|/2)*100 [%] clock input charact eristics table 5 . parameter conditions m in typ m ax unit clock inputs (clk, ) input frequency below 1mhz should be dc - coupled. 0 5 00 mhz input sensitivity, differential 150 mvpp input level, differential 2 vpp i nput common - mode voltage, vcm 1.3 1.57 1.8 v input common - mode range, vcm with 200mvpp signal applied. d c - coupled 1.3 1.8 v input sensitivity, single - ended clk ac - coupled, clk ac - bypassed to rf ground. 150 mvpp input resistance self - biased 3. 2 4.7 6.1 k input capacitance 2 pf
AK8186B sep - 2012 draft - e - 02 - 10 - clock output characteristics table 6 . all specifications at vdd=3.3v ? 5%, vdd_lvpecl= 2.375v to vdd, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions m in typ m ax unit lvpe cl clock output vterm = 50 to output frequency vdd_lvpecl - 2v 10 00 mhz output h i gh voltage(voh) 0xfn[3:2] = 00 (n=0 to 5) 0xfn[3:2] = 01 (n=0 to 5) 0xfn[3:2] = 10 (n=0 to 5) 0xfn[3:2] = 11 (n=0 to 5) vdd_lvpecl - 1. 23 vdd_lvpecl - 0.98 vdd_lvpecl - 0 . 73 v output h i gh voltage(vol) 0xfn[3:2] = 00 (n=0 to 5) vdd_lvpecl - 1.67 vdd_lvpecl - 1.38 vdd_lvpecl - 1.10 0xfn[3:2] = 01 (n=0 to 5) vdd_lvpecl - 1.86 vdd_lvpecl - 1.58 vdd_lvpecl - 1.31 0xfn[3:2] = 10 (n=0 to 5) vdd_lvpecl - 2.03 vdd_lvpecl - 1.77 vdd_lvpec l - 1.49 v 0xfn[3:2] = 11 (n=0 to 5) vdd_lvpecl - 2.20 vdd_lvpecl - 1.94 vdd_lvpecl - 1.65 differential output voltage 0xfn[3:2] = 00 (n=0 to 5) 250 400 550 0xfn[3:2] = 01 (n=0 to 5) 430 600 770 0xfn[3:2] = 10 (n=0 to 5) 550 790 980 mv 0xfn[3:2] = 11 (n=0 to 5) 740 960 1180 lvds clock output output frequency maximum 800 mhz differential output voltage 0x14n[2:1] = 00 (n=0 to 3) 124 180 227 0x14n[2:1] = 01 (n=0 to 3) 247 360 454 mv 0x14n[2:1] = 10 (n=0 to 3) 186 270 340 0x 14n[2:1] = 11 (n=0 to 3) 247 360 454 delta v od 0x14n[2:1] = 01 (n=0 to 3) 25 mv output offset voltage 0x14n[2:1] = 01 (n=0 to 3) 1.125 1.24 1.375 v delta v o d 0x14n[2:1] = 01 (n=0 to 3) 25 mv short - circuit current 0x14n[2:1] = 01 (n=0 to 3) ou tput shorted to gnd. 3.5 24 m a cmos clock outputs output frequency maximum load=10pf 250 mhz output h i gh voltage(voh) ioh=1ma vdd - 0. 2 v output h i gh voltage(vol) iol=1ma 0. 2 v
AK8186B draft - e - 02 sep - 2012 - 11 - timing characteristics table 7 . all specifications at vdd=3.3v ? 5%, vdd_lvpecl= 2.375v to vdd, ta: - 40 to +85 , unless otherwise noted *1) skew: the difference between any two similar delay path s whi le operating a t the same voltage and temperature. *2) differential input through clk/ clk _______ pins : clock input is assumed to be 50% duty. *3) single - end input through clk pin: clock input is assumed to be 50% duty and fout < 150 mhz. parameter symbol conditions min typ max unit lvpecl output termination = 50 to vdd - lvpecl - 2v 0xfn [3:2] = 10 (n=0 to 5) rise/fall time 20% to 80% / 80% to 20% 17 5 2 25 ps propagation delay, clk - to - lvpecl ouput variati on with temperature tbd tbd n s ps/ ? c output skew * 1 same d ivider different d ividers 5 13 40 40 p s ps output duty 750mhz fout 500m fout < 750mhz 250m fout < 500mhz *2 fout < 250mhz * 2 *3 fout<1000mhz , vdd_lvpecl=3.3v ? 5% 30 3 5 40 45 45 50 50 50 50 50 70 65 60 55 55 % % % % % lvds output termination = 100 @3.5ma 0x14n [2:1] = 01 (n=0 to 3) rise/fall time 20% to 80% / 80% to 20% 19 0 350 ps propagation delay, clk - to - lvpecl ouput variation with temperature for all device values tbd tbd n s ps/ ? c output skew *1 same d ivider different d ividers 6 25 62 150 p s ps output duty *2 *3 45 50 55 % cmos output 20% to 80% / 80% to 20% rise/fall time cload = 10pf 40 0 1000 ps propagation delay, clk - to - l vpecl ouput variation with temperature for all device values tbd tbd ns ps/ ? c output skew *1 same divider different dividers 4 28 66 180 p s ps output duty *2 *3 45 50 55 %
AK8186B sep - 2012 draft - e - 02 - 12 - clock output additive phase noise (distribution only; vco divider not used) table 8 . all specifications at vdd=3.3v ? 5%, vdd_lvpecl= 2.375v to vdd, ta: - 40 to +85 , unless otherwise noted param eter m in typ m ax unit test conditions/comments clk - to - lvpecl additive phase noise d o e s not include pll and vco clk=500mhz, output=500m hz, divider=1 input slew rate > 1 v/ns at 1 khz offset at 10 khz offset at 100 khz offset at 1 mhz offset at 10 mhz offset - 108 - 130 - 142 - 149 - 150 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz clk=500m hz, output= 25 0mhz, divider= 2 input slew rate > 1 v/ns at 1 khz offset at 10 khz offset at 100 khz offset at 1 mhz offset at 10 mhz offset - 114 - 133 - 143 - 151 - 152 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz clk - to - lvds additive phase noise does not include pll and vco clk=500mhz, output=500mhz, divider =1 input slew rate > 1 v/ns at 1 khz offset at 10 khz offset at 100 khz offset at 1 mhz offset at 10 mhz offset - 106 - 126 - 141 - 145 - 147 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz clk=500mhz, out put=250mhz, divider=2 input slew rate > 1 v/ns at 1 khz offset at 10 khz offset at 100 khz offset at 1 mhz offset at 10 mhz offset - 114 - 133 - 143 - 150 - 152 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz
AK8186B draft - e - 02 sep - 2012 - 13 - clock output phase noise (internal vco used) table 9 . all specifications at vdd=3.3v ? 5%, vdd_lvpecl= 2.375v to vdd, ta: - 40 to +85 , unless otherwise noted parameter m in typ m ax unit test conditions/comments clk - to - cmos additive phase noise dose not include pll and vco clk=500mhz, output=250mhz, divider=2 input slew rate > 1 v/ns at 1 khz offset at 10 khz o ffset at 100 khz offset at 1 mhz offset at 10 mhz offset - 113 - 135 - 143 - 149 - 152 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz clk=500mhz, output=50mhz, divider=10 input slew rate > 1 v/ns at 1 khz offset at 10 khz offset at 100 khz offset at 1 mhz offset at 10 mhz offset - 129 - 139 - 149 - 156 - 160 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz parameter m in typ m ax unit test conditions/comments lvpecl phase noise through vc o divider and channel divider fvco=2.24256ghz, fout=280.32mhz at 1 khz offset at 10 khz offset at 100 khz offset at 1 mhz offset at 10 mhz offset at 40 mhz offset - 94 - 103 - 105 - 125 - 135 - 136 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz ref=122.88mhz fvco=1.96608ghz, fout=245.76mhz at 1 khz offset at 10 khz offset at 100 khz offset at 1 mhz offset at 10 mhz offset at 40 mhz offset - 89 - 102 - 106 - 127 - 136 - 137 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz ref=122.88mhz fvco=1.75104ghz, fout=218.8 8mhz at 1 khz offset at 10 khz offset at 100 khz offset at 1 mhz offset at 10 mhz offset at 40 mhz offset - 96 - 105 - 108 - 129 - 137 - 138 dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz ref=122.88mhz
AK8186B sep - 2012 draft - e - 02 - 14 - clock output absolute time jitter (clock generation us ing internal vco) table 10 . clock output absolute time jitter (clock generation using external vcxo) table 11 . parameter m in typ m ax unit test conditions/comments lvpecl output absolute time jitter internal vco; through dividers fvco= 1.96608ghz, fout=245.76mhz ref=122.88mhz, pll bw=1 4 0 khz 156 284 fs rms fs rms 200khz to 10mhz 12khz to 20mhz fvco=1.96608ghz, fout=122.88 mhz ref=122.88mhz, pll bw=1 4 0 khz 169 293 fs rms fs rms 200khz to 10mhz 12khz to 20mhz fvco=1.96608ghz, fout=61.44mhz ref=122.88mhz, pll bw=1 4 0 khz 193 325 fs rms fs rms 200khz to 10mhz 12khz to 20mhz parameter m in typ m ax unit test conditions/comments lvpecl output absolute time jitter external vcxo: referenc e = 15.36mhz, r=1 lvpecl=245.76mhz, pllbw=125hz tbd fs rms fs rms fs rms integration bw = 2 00khz to 5 mhz integration bw = 200khz to 10mhz integration bw = 12khz to 20mhz lvpecl=122.88mhz, pllbw=125hz tbd fs rms fs rms fs rms integration bw = 200khz t o 5mhz integration bw = 200khz to 10mhz integration bw = 12khz to 20mhz lvpecl=61.44mhz, pllbw=125hz tbd fs rms fs rms fs rms integration bw = 200khz to 5mhz integration bw = 200khz to 10mhz integration bw = 12khz to 20mhz
AK8186B draft - e - 02 sep - 2012 - 15 - clock output additive time jitter (vco divider not used) table 12 clock output additive time jitter (vco divider used) table 13 parameter m in typ m ax unit test conditions/comments lvpecl output additive time jitter distribution section only clk=500mhz,output=500mhz,divider=1 39 fs rms 12khz to 20mhz clk=500mhz ,output=250mhz,divider=2 92 fs rms 12khz to 20mhz clk=500mhz,output=100mhz,divider=5 137 fs rms 12khz to 20mhz lvds output additive time jitter distribution section only clk=500mhz,output=500mhz,divider=1 76 fs rms 12khz to 20mhz clk=500mhz,o utput=250mhz,divider=2 92 fs rms 12khz to 20mhz clk=500mhz,output=100mhz,divider=5 237 fs rms 12khz to 20mhz cmos output additive time jitter distribution section only clk=500mhz,output=100mhz,divider=5 131 fs rms 12khz to 20mhz parameter m in typ m ax unit test conditions/comments lvpecl output additive time jitter distribution section only clk=500mhz,output=100mhz,divider=5 129 fs rms 12khz to 20mhz lvds output additive time jitter distribution section only clk=500mhz,output=100mhz,divider=5 219 fs rms 12khz to 20mhz cmos output additive time jitter distribution section only clk=500mhz,output=100mhz,divider=5 120 fs rms 12khz to 20mhz
AK8186B sep - 2012 draft - e - 02 - 16 - serial control port table 14 . all specifications at vdd=3.3v ? 5%, vdd_lvpecl= 2.375v to vdd, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit cs ? ih 2.0 v i nput low level v oltage v il 0. 8 v input h i gh level c urrent i ih - 3 3 ? il 45 110 220 ? in 5 pf sclk (input) internal 30k ? ih 2.0 v i nput low level v oltage v il 0. 8 v input h i gh level c urrent i ih 45 110 220 ? il - 3 3 ? in 5 pf sdio (input) i nput high level v oltage v ih 2.0 v i nput low level v oltage v il 0. 8 v input h i gh level c urrent i ih - 3 3 ? il - 3 3 ? in 11 pf sdio, sdo (output) high level o utput voltage v o h s sdo,sdio(out) , i oh = - 1ma 2.7 v low level o utput voltage v ol s sdo,sdio(out) , i ol =1ma 0.4 v timing load=100pf clock rate(sclk) 1/ t sclk 2 0 mhz pulse width high t hi 20 n s pulse width low t lo 20 ns sdio to sclk setup t ds 8 n s sclk to sdio hold t dh 8 n s sclk to valid sdio and sdo t ov 15 n s cs s 12 ns sclk to cs h 8 n s cs pwh 5 n s
AK8186B draft - e - 02 sep - 2012 - 17 - , and table 15 . all specifications at vdd=3.3v ? 5%, vdd_lvpecl= 2.375v to vdd, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit input internal 30k ? ih 2.0 v i nput low level v oltage v il 0. 8 v input h i gh level c urrent i ih - 3 3 ? il 45 110 220 ? in 5 pf reset lo 50 n s sync lo refer to input signal cycle 1.5 c ycle ld, status and refmon table 16 . all specifications at vdd=3.3v ? 5%, vdd_lvpecl= 2.375v to vdd, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit output high level o utput voltage v oh i oh = - 1ma 2.7 v low level o utput voltage v ol i ol =1ma 0.4 v ld output current ild 0x1a[5:0]=04h 0v < ld output voltage < 2v, 88 1 10 132 ?
AK8186B sep - 2012 draft - e - 02 - 18 - t iming d iagrams figure 3 . lvpecl timing, differential figure 4 . lvds timing, differential figure 5 . cmos timing, single - ended, 10pf load figure 6 . serial control port - read - figure 7 . serial control port - write -
AK8186B draft - e - 02 sep - 2012 - 19 - t heory of operation operational configuration s t he AK8186B can be configured in two ways below. ? internal vco and clock distribution ? external vco and clock distribution each functional block must be set by the registers through a serial control port. internal vco and clock distribution when using the internal vco and pll, the things below are to be cared. - prescaler divid e ratio : 8/9, 16/17 and 32/33 can be used to meet the maximum input frequency of a,b counter, 300mhz. - vco calibration must be executed after the internal vco is enabled. table 17 settings for internal vco register function 0x10[1:0] = 00b pll normal operation (pll on). 0x10 to 0x1e pll settings. select and enable a reference input; set r, n(p,a,b) pfd polarity, and icp according to the intended loop configurati on . 0x18[0] = 0 reset vco calibration. 0x232[0] = 1 register update. 0x18[0] = 1 initiate vco calibration. 0x232[0] = 1 register update. 0x1e0[2:0] set vco divider ratio . 0x1e1[0] = 0 use the vco divider as source for distribution section . 0x1e1[1 ] = 1 select vco as the source. figure 8 internal vco and clock distribution
AK8186B sep - 2012 draft - e - 02 - 20 - external vco and clock distribution when using the external vco and pll, the things below are to be cared. - prescaler divide ratio : 1, 2/3, 4/5, 8/9, 1 6/17 and 32/33 can be used to meet the maximum input frequency of a,b counter, 300mhz. - maximum frequency of the external vc x o is 500mhz. table 18 settings for external vco register function 0x10[1:0] = 00b pll normal operation (pll on). 0x10[7] = 0 or 1 pfd polarity 0: positive 1:negative 0x10 to 0x1e pll settings. select and enable a reference input; set r, n(p,a,b) pfd polarity, and icp according to the intended loop configuration . 0x1e0[2:0] set vco divider ratio. 0x1e1[0] = 0 or 1 select the source for distribution section. 0: vco divider 1: clk input 0x1e1[1] = 0 select the clk input as the source. figure 9 external vco and clock distribution
AK8186B draft - e - 02 sep - 2012 - 21 - pll the AK8186B integrates a pll with a vco w hich can be configured to meet users application . the following functions are set through a serial control port. the setting registers are mapped into 0x10 to 0x1f in a register. - pll power down - charge pump current - r counter for reference input - a counter, b counter and prescaler in loopback path - pin function of status, ld and refmon pins - vco calibration - lock detect - frequency monitor of ref1, ref2 and vco - switchover - holdover figure 10 . pll r eference input the reference input sec tion of the AK8186B allows a differential input or two single - ended inputs. both types of inputs are self - biased. it allows easy ac - coupled input signals. the desired reference input is selected by 0x1c [2:0] . single - ended input a dc - coupled cmos level sig nal or an ac - coupled sinewave or square wave signal can be input. differential input an ac - coupled signal or a dc - coupled signal can be input. if a single - ended signal is applied to the differential refin, the refinn should be decoupled through a capacito r to a ground. note a ll reference inputs are powered down by default. when pll is powered down, all the reference inputs are powered down. when the differential mode is select ed , the singl e - ended inputs are powered down and vice versa.
AK8186B sep - 2012 draft - e - 02 - 22 - the maximum input f requency of both type of inputs is 250mhz. reference switchover when dual single - ended cmos inputs are imposed to ref1 and ref2, the AK8186B could support automatic and manual pll reference clock switching between ref1 and ref2. the automatic switc hover i s enabled by setting 0x1c [4] . 0x1c [4] = 0 : manual switchover 1 : automatic switchover note; the single - ended inputs should be dc - coupled cmos levels and not go to high impedance . if these go to high impedance, input buffers may cause chattering due to noise. a false detection might occur . manual switchover a pll referenc e input can be selected by a register or a pin. 0x1c [5] assigns the register 0x1c [6 ] or the ref_sel pin to select a pll reference input . automatic switchover automatic switchover has two modes of operation. both of them switch from ref1 to ref2 when ref1 is lost. the difference of the two modes is whether the AK8186B would stay on ref2 or not when ref1 returns. 0x1c [3] selects one of the two modes . 0x1d [3] = 0 : switch to ref 1. 1 : stay on ref2. it can be switched to ref1 manually. condition to switch from ref1 to ref2 if the referenc e switchover circuit detects three consecutive rising edge s of ref2 without any ref1 rising edges, the ref1 is considered to be lost. on the 2nd su bsequent rising edge of ref2, t he reference clock input to pll is switc hed from ref1 to ref2 . condition to switch back to ref 1 when 0x1d [3] =0 if the reference switchover circuit detects four consecutive rising edge s of ref 1 without three consecutive ref 2 r ising edges between ref1 edges , the ref1 is considered to be returned . on the 2nd subsequent rising edge of ref2, the reference clock input to pll is switched from ref2 to re f1 . r divider (reference divider) the reference input goes into the r divider ( a 14 - bit counter). it can be set to any value from 0 to 16383 by 0x11 and 0x12. when 0 is set, the input is divided by 1. maximum output frequency the output of the r divider goes to one of the pfd inputs which is compared to the output of the n divider. t he frequency appl ied to the pfd must not exceed 100mhz. reset the r is divider can be reset under the following conditions. 1) power on reset 2) when reset is asserted low. 3) when 0x16 [6] is set to 1 (reset of the r divider) 4) when 0x16 [5] is set to 1 (shared rese t bit of the r, a and b counter) 5) when sync is released from l to h.
AK8186B draft - e - 02 sep - 2012 - 23 - phase frequency detector (pfd) the pfd has two inputs of r divider and n divider. it outputs an up/down signal for the charge pump, which is proportional to the phase and frequency diff erence between the inputs. both input frequencies must not exceed the maximum frequency of 100mhz. charge pump (cp) the charge pump pumps up/down controlled by the output of the pfd. the output current of the cp goes out through the cp pin and integrated a nd filte red by the external loop filter, then is finally turned into a voltage. the voltage goes into the vco via the lf pin to tune the vco frequency. the cp has four mode s of operation and eight current values. each of them can be set by the registers b elow. table 19 register for charge pump operation mode item register description operation mode 0x10 [3:2] normal, high impedance, pump up, pump down cp current 0x10 [6:4] 0.6 to 4.8 ma with 0.6ma step (cp rset=5.1 k ) on - chip vco t he AK8186B integrates a vco working in the range of 1.75g hz to 2.25g hz. the vco requires a calibration to achieve optimal operation around the refin frequency. after power - up or reset. a initial calibration is required along with the procedure shown below. the calibration can be executed at anytime after power - up or reset from the step marked (*). sync function is executed during the vco calibration. distribution outputs remain static in this period. maximum time of the vco calibration is 4400 cycle s of a v co calibration clock supplied by a vco calibration divider. the vco calibration divider divides the r divider output (= the pfd input clock) with the divider value of 2,4,8 or 16 set to 0x18 [2:1] . when the calibration is finished, a logic true (1b) is retu rned to a readback bit 0x 1f [6] . figure 11 . procedure of vco calibration s e t t h e p l l r e g i s t e r s t o t h e p r o p e r v a l u e s f o r t h e p l l l o o p . i n i t i a t e v c o c a l i b r a t i o n 0 x 1 8 < 0 > = 0 0 x 2 3 2 < 0 > = 1 ( u p d a t e r e g i s t e r s ) 0 x 1 8 < 0 > = 1 0 x 2 3 2 < 0 > = 1 ( u p d a t e r e g i s t e r s ) v c o c a l i b r a t i o n f i n i s h e s . i n t e r n a l s y n c s i g n a l i s r e l e a s e d . t h e o u t p u t s s t a r t c l o c k i n g . v c o c a l i b r a t i o n s t a r t s . a s y n c f u n c t i o n s t a r t s . o u t p u t s g o e s i n t o s t a t i c s t a t e . s e t s t h e p l l t o p r o p e r v a l u e s . t h e p l l l o c k s . a f t e r p o w e r - u p o r r e s e t . ( * )
AK8186B sep - 2012 draft - e - 02 - 24 - external vco/vcxo the AK8186B supports an external vco/vcxo. the clk/clk input can be used as a differential feedback for an ext ernal vco/vcxo. the input frequency is up to 500mhz. pll external loop filter the loop filter supplies a voltage to the vco via the lf pin to move the vco frequency up or down. when using the internal vco, the external loop filter should be referenced to the bypass pin for optimal noise and spurious performance. an example is shown in fig.13. the values of loop filter must be calculated for each pll. it depends on the vco frequency, the kvco, the pfd frequency, the cp current, the desired loop bandwidth an d the desired phase margin. figure 12 example of external loop filter for the internal vco figure 13 example of external loop filter for an external vco feedback divider (n divider) the n divider consists of a prescaler (p), a and b counters. figure 14 . n divider p rescaler th e prescaler is a dual modulus counter which has two modes of operation . d ivision value of a counter defines the mode as below . 1) when a = 0 : a fixed divide (fd) mode where the prescaler divides by p. 2) when a ? 0: dual modulus (dm) mode where the prescaler divides by p and (p+1).
AK8186B draft - e - 02 sep - 2012 - 25 - since the maximum output frequency of the prescaler is 300mhz, the prescaler input frequency is limited by the mo des as shown in table 4 . the prescaler must divide its input frequency by appropriate divide ratio defined by register 0x016[2:0] . in case of using the internal vco , its output ( 1.75g hz min) must be divided by p = 8, 16 and 32. (see the pll configuration in register map function descriptions ) fd mode (a=0) the prescaler divider value is p. it is divided by b counter. n = p x b where p = 1, 2, 4, 8, 16 or 32 for an external vco/vcxo. p = 8, 16 or 32 for an internal vco. b : 3 to 819 1 when b = 1, b cou nter is bypassed. not allowed for b = 0 and 2. dm mode (a ? 0) the prescaler divider value is p for (b - a ) times and p+1 for a times . n = p x b + a where p = 1, 2/3, 4/5, 8 /9 , 16 /17 or 32 /33 for an external vco/vcxo. p = 8 /9 , 16 /17 or 32 /33 for an internal vco. b : 3 to 819 1 when b = 1, b counter is bypassed. not allowed for b = 0 and 2. the output frequency of the n divider f vco /n is equated to the output of the r divider f ref /r at the pf d. then the vco frequency is 1) when a = 0: f vco = f ref x n/r where n = p x b 2) when a ? 0: f vco = f ref x n/r where n = p x b + a a and b counters the division value of the a and b counter s is defined by the register s below. a counter : 0x13 [5:0] b counter : 0x14[ 7 :0] and 0x15[ 4 :0] note ; - both divi sion values should be s et a b. - p = 1, 2, 4, 8, 16 or 32 when a=0. - b = 0 and b = 2 are not allowed. - maximum input frequency of a/b counters is 300mhz. reset counters sync pin resets all of p, a and b counters simultaneously. this is allowed by t he register 0 x19[7:6] . a /b counters can be reset by the register 0x 16 [5][4] .
AK8186B sep - 2012 draft - e - 02 - 26 - lock detect the AK8186B has three kinds of lock detect function . each lock detect function is able to report to ld, status and refmon pins. . table 20 registers for lock detec t mode enable/disable register output pin ld 0x1a [5:0] status 0x17[ 7:2 ] refmon 0x1b<4:0> digital lock detect (dld) 0x18 [3] ? ? ? ? ? digital lock detect (dld) the digital lock detect fun ction detects a lock when the phase difference of the rising edges at the pfd inputs is less than the lock detect window (3.5 ns typical). the lock is indicated when the number of consecu tive lock detection reaches the threshold of the lock detect counter defined by 0x18<6:5> . the unlock is indicated when the dld function detects the larger phase differen ce at the pfd inputs than the lock detect window. the unlock threshold is just one value . figure 15 . digital lock detect c urrent source digital lock detect (cld) the lock indication by the dld is normal ly not stable until the pll gets in lock completely. in s ome application , it might be require d to get a lock detect after the pll gets solidly locked. the current source dld fu nction (cld) could be useful for that requirement. the cld provides a current of 110ua to ld pin when the d ld detects a lock (dld = h) . while the pll continues to be in lock state, the voltage of ld is going up with the cu rrent. but if the pll is back to unlock state, the charge on a capacitor externally connected to ld is discharged instantly. the voltage of ld can be sensed by an internal or external comparator. when the internal ld pin comparator is used (0x1d [3] =1b) , its output can be read at status pin (0x17[7:2] ) or refmon pin
AK8186B draft - e - 02 sep - 2012 - 27 - (0x1b[4:0] ) . selecting a properly value of capacitor allows a lock detect indication to be delayed . the ld pin comparator trip point is shown in table 1 6 . figure 16 . curr ent source lock detect analog lock detect (ald) when 0x1a [5:0] is set to the value shown below , the analog lock detect is indicated at the ld pin. the ald function requires a external r - c filter to indicate lock/unlock state. 0x1a [5:0] = 01h : p - chann el open drain ald (active low) 0x1a[5:0] = 02h : n - channel open drain ald (active high) figure 17 . analog lock detect (n/p - channel open drain) n - channel open drain the ald si gnal is derived from t h e up/down control outputs of the pfd. ? when the pll is in lock, the ald signal is mainly low with minimum high - going pulse. this leads the vol tage of ld to getting up to vdd. ? when the pll in in unlock, the ald signal has a wider high - going pulse. this lea ds the vo ltage of ld to getting down to ground. p - channel open drain the ald signal is the inverting of the ald. ? when the pll is in lock, the ald signal is mainly high with minimum low - going pulse. this leads the voltage of ld to getting down to ground. ? w hen the pll in in unlock, the ald signal has a wider high - going pulse. this leads the vo ltage of ld getting up to vdd . d l d l d p i n c o m p a r a t o r 1 1 0 a 3 0 0 l d r e f m o n o r s t a t u s a k 8 1 8 6 b c a k 8 1 8 6 b a l d r 1 r 2 c v o u t v d d = 3 . 3 v l d a k 8 1 8 6 b a l d r 1 r 2 v o u t l d c
AK8186B sep - 2012 draft - e - 02 - 28 - holdover some application requires holding t he output frequency to be constant even though the ref input is lost out . a h oldover functi on is for such a requirement. in the AK8186B , the holdover function puts the charge pump into high - impedance state so that the vco keeps its frequency constant. however, any leakage could occur at the charge pump output, which leads the unwanted vco freque ncy shift. adequate capacitive value in the loop filter should be selected to avoid shifting the vco frequency out of the required limit. the AK8186B has two mode s of holdover function , manual or auto matic mode . manual holdover is activated by the sync pin. automatic holdover is activated by the voltage of ld pin. both holdover modes are enabled with 0x1d [2:0] . table 21 setting holdover mode holdover enable 0x1d [2] mannual/automatic 0x1d [1] holdover enable 0x1d [0] manual holdover 1 1 1 automatic holdover 1 0 1 manual holdover mode a manual holdover put s the charge pump into a high impedance state immediately when the sync pin is asserted low. this is trigged by the falling edge of the sync . getting into the holdover condit ion : the falling edge of the sync operation timing : immediately operation : put s the charge pump into a high impedance state leaving the holdover condition : the sync = high operation timing : synchronous with the first pfd risi ng edge after the s ync goes high. operation : puts the charge pump into a normal state , resets the b - counter. figure 18 . manual holdover note : set the channel divider to ignore the sync pin at least after an initial sync event . otherwise, ever y time sync is asserted low to invoke the manual holdover , the distribution outputs become dc output state .
AK8186B draft - e - 02 sep - 2012 - 29 - table 22 setting the channel divider to ignore the sync divider nosync register bit value to ignore sync automatic holdover mode an automatic holdover puts the charge pump into a high impedance state immediately when the unlock state is detected. a flow chart of the automatic holdover function is shown in figure 16 . getting into the holdover condition : ld pin = h when dld = low (false) operation timing : immediately operation : puts the charge pump into a high impedance state leaving the holdover condition : dld = high (true) operati on timin g : synchronous with a first pfd rising edge after dld goes high. operation : puts the charge pump into a normal state, resets the b - counter. ld pin is able to report the status of dld, ald and cld. the cld is recommended to use for the automatic holdover to avoid re - triggering a holdover due to chattering on the ld. the register 0x1a [5:0] defines the function of the ld. the auto holdover function uses the ld pin comparator to sense the status of the ld pin. when the register 0x1d [3] =0, the ld comparator is disabled and the ld pin is treated as always high by the automatic holdover function. when 0x1d [3] = 1, the ld comparator is enabled and can be used for dld, ald and cld. the registers shown in table are required to be set to use the automatic holdover f unction. table 23 setting automatic holdover function register name description 0x18<6:5> lock detect counter select pfd cycles to determine lock. 0x18 [3] disable digital lock detect set 0 to operate normally. 0x1a [5:0] ld pin c ontrol set 04h to select current source lock detect if using the ld pin comparator. 0x1d [3] ld pin comparator enable set 1 if using. when set 0 (disabled), the automatic holdover function treats the ld pin as always high. 0x1d [1] external holdover contro l set 0 to use the automatic holdover function. 0x1d [2][0] holdover enable set 1 to enable holdover.
AK8186B sep - 2012 draft - e - 02 - 30 - figure 19 . automatic holdover frequency status monitors the AK8186B has a frequency status monitor to indicate if the ref1/ 2 and the vco frequency below a threshold frequency . there are two threshold frequencies such as n ormal and extended for ref1/2 . the vco frequency is monitored at the output of the prescaler. table 24 setting frequency status monito rs monitored signal monitor enable register minimum threshold frequency status indication register vco 0x1b [7] =1 0 . 5 mhz 0x1f [3] ref2 0x1b [6] =1 normal 0 . 5 mhz (0x1a [6] =0) extended 4 khz (0x1a [6] =1) 0x1f [2] ref1 0x1b [5] =1 0x1f [1]
AK8186B draft - e - 02 sep - 2012 - 31 - clock distri bution vco divider the vco divider provides frequency division between the internal vco and the clock distribution section. the vco divider can be set to divide by 2,3,4,5 and 6 (0x1e0 [2:0] ) . the output of the vco divider has 50% duty even though the divis ion is 3 and 5 due to the duty cycle compensation circuit. vco divider can be bypassed when using an external vco/vcxo. when bypassed, the input duty through clk / clk _______________ pins is not compensate d. c hannel d ividers for lvpecl o utputs there are three channel dividers for lvpecl outputs. each divider drives a pair of lvpecl outputs. the divider value dx can be set 1 to 32. dx : m + n +2 (m,n : 0 to 15, dx = 1 when the bypass bit is set.) table 25 registers for lvpecl channel divider 0,1 and 2 channel divider low cycles m high cycles n bypass lvpecl outputs 0 0x190 [7:4] 0x190 [3:0] 0x191 [7] out0, out1 1 0x193 [7:4] 0x193 [3:0] 0x194 [7] out2, out3 2 0x196 [7:4] 0x196 [3:0] 0 x197 [7] out4, out5 the divider has the duty cycle correction . it always operates and outputs 50% duty clocks. c hannel d ividers for lvds/cmos outputs there are two channel dividers for lvds/cmos outputs. each divider drives a pair of lvds outputs(or two pair of cmos outputs). the divider value dx can be set 1 to 32. dx : m + n +2 (m,n : 0 to 15, dx = 1 when the bypass bit is set.) table 26 registers for lvpecl channel divider 3 and 4 channel divider low cycles m high cycles n bypass lvds/lvcmos outputs 3 3.1 3.2 0x199 [7:4] 0x19b [7:4] 0x199 [3:0] 0x19b [3:0] 0x19c [4] 0x19c [5] out6 (a, b), out7 (a, b) 4 4.1 4.2 0x19e [7:4] 0x1a0 [7:4] 0x19e [3:0] 0x1a0 [3:0] 0x1a1 [4] 0x1a1 [5] out8 (a, b), out9 (a, b) the divider has the duty cycle correct ion . it always operates and outputs 50% duty clocks.
AK8186B sep - 2012 draft - e - 02 - 32 - s ynchronizing the o utputs : sync function the AK8186B clock outputs can be synchronized to each other . t he sync function starts to operate by the following conditions. 1) the pin is forced low and then released (m anual sync). 2) by setting an d then resetting t he soft sync bit 0x230 [0] 3) after a vco calibration is completed. the channel divider output status depends on the register setting of the channel divider such as bypass bit, nos ync bit, force high bit, start high bit and phase offset bits. figure 20 . sync timing sync function can be disabled by nosync bit . when the nosync bit is set to 1, t he sync function is disabled. tab le 27 sync disable on channel divider channel divider nosync bit 0 0x191[6] 1 0x194[6] 2 0x197[6] 3.1, 3.2 0x19c[3] 4.1, 4.2 0x1a1[3] p hase o ffset each channel divider has a programmable phase offs et function. phase offset m eans a delay to rising edge of output clock from zero offset output. t wo kinds of bits such as start high bit and phase offset bits affect total p hase o ffset . t he phase offset is effective when the sync function is invoked . table 28 start high and phase offset registers on channel divider channel divider start high phase offset 0 0x191 [4] 0x191 [3:0] 1 0x194 [4] 0x194 [3:0] 2 0x197 [4] 0x197 [3:0] 3.1 0x19c [0] 0x19a [3:0 ] 3.2 0x19c [1] 0x19a [7:4 ] 4.1 0x1a1 [0] 0x19f [3:0] 4.2 0x1a1 [1] 0x19f [7:4] sync s y n c b p i n i n p u t t o c h a n n e l d i v i d e r i n p u t t o v c o d i v i d e r 1 4 o r 1 5 c y c l e s a t c h a n n e l d i v i d e r s t a r t l o w 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 o u t p u t o f c h a n n e l d i v i d e r s t a r t h i g h o u t p u t o f c h a n n e l d i v i d e r
AK8186B draft - e - 02 sep - 2012 - 33 - when the start high bit =1, the default phase offset exists before the phase offset defined by the phase offset bits . the default phase offset varies depending on the divider ratio. when the divider is bypassed, the default offset is equal to zero. total phase offset = default phase offset + phase offset bits d efault p hase o ffset start high bit = 0 : zero start high bit = 1 : roundup(divider ratio/2) where divider ratio >=2 example; divider ratio = 3, phase offset bits = 2, then defau lt phase offset = 2 total phase offset = 2 + 2 = 4 clock cycles figure 21, 22 shows how those offsets work. figure 21 . channel divider phase offset with start high bit = 0 (start low) figure 22 channel divider phase offset with start high bit = 1 (start high) s y n c b p i n i n p u t t o c h a n n e l d i v i d e r i n p u t t o v c o d i v i d e r s t a r t l o w 1 2 1 4 1 5 o u t p u t o f c h a n n e l d i v i d e r s t a r t h i g h = 0 d i v i d e r a t i o = 2 p h a s e o f f s e t = 0 t o t a l p h a s e o f f s e t = 0 + 0 = 0 t o t a l p h a s e o f f s e t = 0 + 1 = 1 t o t a l p h a s e o f f s e t = 0 + 2 = 2 t o t a l p h a s e o f f s e t = 0 + 0 = 0 t o t a l p h a s e o f f s e t = 0 + 1 = 1 p h a s e o f f s e t = 1 p h a s e o f f s e t = 2 p h a s e o f f s e t = 1 t o t a l p h a s e o f f s e t = d e f a u l t p h a s e o f f s e t + p h a s e o f f s e t ( b y r e g i s t e r b i t s ) s t a r t h i g h = 0 d i v i d e r a t i o = 2 p h a s e o f f s e t = 1 s t a r t h i g h = 0 d i v i d e r a t i o = 2 p h a s e o f f s e t = 2 s t a r t h i g h = 0 d i v i d e r a t i o = 3 p h a s e o f f s e t = 0 s t a r t h i g h = 0 d i v i d e r a t i o = 3 p h a s e o f f s e t = 1 s y n c b p i n i n p u t t o c h a n n e l d i v i d e r i n p u t t o v c o d i v i d e r p h a s e o f f s e t = 1 s t a r t h i g h 1 2 1 4 1 5 o u t p u t o f c h a n n e l d i v i d e r d e f a u l t p h a s e o f f s e t = 1 t o t a l p h a s e o f f s e t = d e f a u l t p h a s e o f f s e t + p h a s e o f f s e t ( b y r e g i s t e r b i t s ) t o t a l p h a s e o f f s e t = 1 + 0 = 1 t o t a l p h a s e o f f s e t = 1 + 1 = 2 t o t a l p h a s e o f f s e t = 1 + 2 = 3 t o t a l p h a s e o f f s e t = 2 + 0 = 2 t o t a l p h a s e o f f s e t = 2 + 1 = 3 p h a s e o f f s e t = 1 p h a s e o f f s e t = 2 d e f a u l t p h a s e o f f s e t = 2 s t a r t h i g h = 1 d i v i d e r a t i o = 2 p h a s e o f f s e t = 0 s t a r t h i g h = 1 d i v i d e r a t i o = 2 p h a s e o f f s e t = 1 s t a r t h i g h = 1 d i v i d e r a t i o = 2 p h a s e o f f s e t = 2 s t a r t h i g h = 1 d i v i d e r a t i o = 3 p h a s e o f f s e t = 0 s t a r t h i g h = 1 d i v i d e r a t i o = 3 p h a s e o f f s e t = 1
AK8186B sep - 2012 draft - e - 02 - 34 - lvpecl outputs : out0 to out5 the AK8186B has three pair of lvpecl buffers. each pair has dedicated vdd supply pin, vdd _lvpecl, allowing fo r a sepa rate power supply to be used. vdd _lvpecl can be from 2.5v to 3.3v. figure 23 . lvpecl equivalent circuit lvds/ cmos outputs : out6 to out9 out6 to out9 can be configured as an lvds output or a pair of cmos output s. figure 24 . lvds/cmos equivalent circuit table 29 lvpecl outputs control regi ster control item register invert polarity 0xf0 to f5 [4] differential voltage 0xf0 to f5 [3:2] power down* 0xf0 to f5 [1:0] *)lvpecl outputs hi - z. there are two modes of power down. - partial power down - power down in partial power down, an out put stage is off but a differential input stage is on. table 30 lvds/cmos outputs control register control item register output polarity 0x140 to 143 [7:5] cmos b turn on/off 0x140 to 143 [4] select l vds/cmos 0x140 to 143 [3] lvds output current 0x140 to 143 [2:1] power down* 0x140 to 143 [0] *)lvds outputs hi - z. cmos outputs low. output stage differential input stage
AK8186B draft - e - 02 sep - 2012 - 35 - reset the AK8186B has three types of reset as below. 1) power - o n reset 2) asynchronous reset by reset pin 3) soft reset by 0x00 [5] power - on reset (por) at power on, a n internal power - on reset signal is generated which initializes the register to the default settings. note that the AK8186B does not execute the sync operation after power - on reset. t o synchronize the clock outputs by sync function after power - up , syn c _b pin must be released more than 0.5 s after starting a vco calibration. figure 25 . recommended power - up sequence asynchronous reset by pin when the reset pin is asserted, the AK8186B is imm ediately initialized to t he default settings. soft reset by 0x00 [5] when the soft reset bit s 0x00 [5] and [2] are set to 1, the AK8186B is immediately initialized to the default settings except the soft reset bit s without setting the update register 0x232 [0] to 1. both soft reset bits must be cleared by setting 0 since they are not self - cleaning bits. vdd por reset ____________ pin register access is effective 1 s after the vdd rises over 3.135v. register access 1.575v typ por on por off 1 s 3.135v por theshold disable e nable pll status power down power on u pdate registers (0x232[0] =1) c a libration u pdate registers sync __________ pin 0.5 s sync _ _________ pin must be released more than 0.5 s after a vco calibration .
AK8186B sep - 2012 draft - e - 02 - 36 - power down modes the AK8186B has two modes of power down. 1) chip power down 2) block power down (pl l , ref1/2, vco, vco divider, clk input , out0 to 9) chip power down by pdn pin operatio n : p uts a ll the blocks except the bias to the analog block into power down mode. condition : pdn pin is asserted low operation timing : immediately note : t he registers are not reset. serial control port is active. if the AK8186B clock outputs must be s ynchronized to each other, a sync is required upon exiting power down (see the synchronizing the outputs C sync function ). a vco calibration is not required when exiting power down. pll power down operation : the pll goes into power - down. condition : wri te 0x10 [1:0] = 01b or 11b, then updates the register ( 0x232 [0] =1b). operation timing : asychronous power - down mode : 0x10 [1:0] = 01b immediately after the register update is executed. synchronous power - down mode : 0x10 [1:0] = 11b synchronized w ith the up/down signal for the cp after the register update is executed. this is for preventing the unwanted frequency jumps. ref1, re f 2 power down operation : the ref1and/or ref2 goes into power - down. condition : ref1: write 0x1c [1] = 0b, then updates the register ( 0x232 [0] =1b). ref2: write 0x1c [2] = 0b, then updates the register ( 0x232 [0] =1b). operation timing : immediately after the register update is executed. note : the ref1/ ref2 can not be powered down when automatic switchover is active . vco and clk input power down operation : the vco, vco divider and clk input section can be power down by 0x1e1[4:1]. . condition : set 0x1e1 [4:1 ] to the adequate value depending on your need , then updates the register ( 0x232 [0] =1b). see the register ma p function description of vco, vco divider and clk input register (0x1e1). operation timing : immediately after the register update is executed. distribution power down operation : all of output buffer s go into power - down. condition : write 0x230[1] = 1b, then updates the register ( 0x232[0] =1b). operation timing : immediately after the register update is executed.
AK8186B draft - e - 02 sep - 2012 - 37 - individual clock output power down (out0 to out9) operation : any of the clock outputs goes into power - down. condition : write the appro priate registers below, then updates the register ( 0x232 [0] =1b). operation timing : immediately after the register update is executed. table 31 power down register for outputs output port register lvpecl out0 0xf0 [1:0] out1 0xf 1 [1:0] out2 0xf2 [1:0] out3 0xf3 [1:0] out4 0xf4 [1:0] out5 0xf5 [1:0] lvds/ cmos out6 0x140 [0] out7 0x141 [0] out8 0x142 [0] out9 0x143 [0]
AK8186B sep - 2012 draft - e - 02 - 38 - serial control port the AK8186B has a 3 or 4 - wire serial control port which is compatible with both the motorola spi ? and intel ssr ? protocols. the function of the serial control port is as follows. - read/write access to all registers - s ingle/multiple byte access - msb/lsb first transfer format - data output on sdio pin (3 - wire access : default ) or sdo pin (4 - wire access) - l ong instruction only (16 bits) serial control port pin descriptions figure 26 . serial contro l port table 32 serial control port pin descriptions pin no. pin name descriptions 16 sclk serial clock i nput. write data bits are sampled at the rising edge of this clock. read data bits are sampled at the falling edge of this clock. pulled down by an internal 30k ? cs cs cs ? general description of serial control port the following section describes the function of the serial control port. communication cycle serial communica tion cycle consists of two parts. the first one is a 16 - bit instruction section . t he second one is a data section . m ultibyte data can be transferred . figure 27 . serial port communication cycle sdio 16 - bit instruction w ord data byte 1 data byte 2 data byte n
AK8186B draft - e - 02 sep - 2012 - 39 - since the AK8186B supports only the long instruction (16 bits) mode, the register 0x00 [4:3] must be 11b. the instruction word (16 bits) the instruction consist s of 3 parts; read/write command, byte to transfer and address. see below. msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12=0 a11=0 a10=0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 figure 28 . 16 - bit instruction word table 33 16 - bit instruction word bit name description i15 r/ w table 34 byte transfer count w1 w0 byte to tran sfer 0 0 1 0 1 2 1 0 3 1 1 s treaming mode streami ng mode is to transfer more than three bytes. it does not skip over reserved or blank registers. write when i15=0, write operation is executed. the timing chart of 2 - byte data write is shown below. wr ite data is sampled at the rising edge of sclk. figure 29 . serial contorl port - write - msb first write in streaming mode when data is transferred in streaming mode, the reserved and blank registers are not skipped over. any d ata written to those registers does not affect the operation of the AK8186B . update register the serial control port has a two - step registers. it consists of a buffer register and an active register. when data is transferred to the serial control port, th e data is written into the buffer register. at this point, the written data is not active. to make this data active, an update register operation is needed. when set 0x232 [0] =1, the data in the buffer register is transferred to the active register. this is called update register and makes the data active. any number of data can be written into the buffer register before executing the update register. 0x232 [0] is self - clear bit register.
AK8186B sep - 2012 draft - e - 02 - 40 - figure 30 . buf fer/active register t h e serial control port configuration registers of 0x00 and 0x04 does not require the update register. the written data is immediately effect ive . read when i15=1, read operation is executed. the timing chart of 3 - byte data read is sho wn below. read data is valid at the falling edge of sclk. figure 31 . serial control port - read - msb first the serial control port can read back the data in the buffer registers or in the active registers. 0x04 [0] selects whic h register is read. figure 32 . readback registers read in streaming mode when data is transferred in streaming mode, the reserved and blank registers are not skipped over. bidirectional/unidirectio nal mode by default, the serial control port operates in the bidirectional mode. both write data and readback data are transferred on the sdio pin. in unidirectional mode, the readback data is on the sdo pin. 0x00 [7][0] enables the sdo pin. bus stalling in read/write access s c l k s d o s d i o s e r i a l c o n t r o l p o r t b u f f e r r e g i s t e r s a c t i v e r e g i s t e r s u p d a t e r e g i s t e r s u p d a t e r e g i s t e r o p e r a t i o n i s e x e c u t e d w h e n s e t 0 x 2 3 2 < 0 > = 1 . c s s c l k s d o s d i o s e r i a l c o n t r o l p o r t b u f f e r r e g i s t e r s a c t i v e r e g i s t e r s r e a d b a c k o f t h e b u f f e r r e g i s t e r s o r t h e a c t i v e r e g i s t e r s c s
AK8186B draft - e - 02 sep - 2012 - 41 - when 1, 2 or 3 - byte transfer, but not streaming, cs can rise up on boundary of every data byte to stall the bus. while cs is high, read/write operation is suspended and the state machine of the serial control port stays in wait sta te . the operation resumes after cs goes down. figure 33 . bus stalling if the system gets out of the wait state, the state machine should be reset by the following procedure. return cs low and c omplete the transfer of remai ned data. return cs low for at least one complete sclk cycle (but less than 8 cycles). if cs goes high on non - boundary area, the read/write access is immediately cancelled. msb/lsb first t ransfers the AK8186B serial control port transfer the data by msb first or lsb first. 0x00 [6][1] selects one of which. default is msb first . msb first the instruction and data are transferred f r o m msb. when the AK8186B executes multibyte access , the address included in the instruction is the start address. address decrement s at every data byte access. figure 34 . msb first transfers
AK8186B sep - 2012 draft - e - 02 - 42 - lsb first the instruction and data are transferred from lsb. when the AK8186B executes multibyte access, the address included in the instruction is the st art address. address in crement s at every data byte access. figure 35 . lsb first transfers in both msb and lsb first modes, streaming mode stops at the address of 0x232. note that the reserved and blank registers are not skipped . table 35 stop sequence in streaming mode mode address direction stop sequence lsb first increment 0x 230, 0x 231, 0x 232, stop msb first decrement 0x 001, 0x 000, 0x 232, stop the serial control port is configured by the register 0 x00 [7:4] . 0x00 [3:0] should be mirrored to 0x00 [7:4] . t his makes it no matter whether the data is written from msb or lsb .
AK8186B draft - e - 02 sep - 2012 - 43 - r egister map addr (hex) parameter bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value serial control port 00 serial po rt configuration sdo active lsb first soft reset long instruction long instruction soft reset lsb first sdo active 18 01 blank 02 reserved 03 part id (read only) 43 04 read b a ck control blank read back active registers 00 pll 10 pfd & cp pfd polar ity charge pump current charge pump mode pll power down 7d 11 r counter 14 - bit r divider bits <7:0> 01 12 blank 14 - bit r divider bits <13:8> 00 13 a counter blank 6 - bit a counter 00 14 b counter 13 - bit b counter bits <7:0> 03 15 blank 13 - bit b counter bits<12:8> 00 16 pll control 1 s e t cp pin t o vdd/2 reset r counter reset a&b counters reset all counters b counter bypass prescaler p 06 17 pll control 2 status pin control reserved 00 18 pll control 3 reserved lock detect counter digital lock detect wi ndow disable digital lock detect vco calibration divider vco cal now 06 19 pll control 4 r,a,b counters sync pin reset reserved reserved 00 1a pll control 5 reserved reference frequency monitor threshold ld pin control 00 1b pll control 6 vco frequen cy monitor ref2 frequency monitor ref1 frequency monitor refmon pin control 00 1c pll control 7 blank select ref2 use ref_sel pin automatic reference switchover stay on ref2 ref2 power on ref1 power on differential reference 00 1d pll control 8 reserved pll status register disable ld pin comparator enable holdover enable external holdover control holdover enable 00 1e pll control 9 reserved 00 1f pll readback reserved vco cal finished holdover active ref2 selected vco frequency threshold ref2 frequency threshold ref1 frequency threshold digital lock detect -- 20 to 4f blank
AK8186B sep - 2012 draft - e - 02 - 44 - addr (hex) parameter bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value a0 blank reserved 01 a1 blank reserved 00 a2 blank reserved 00 a3 blank reserved 01 a4 blank reserved 00 a5 blank reserved 00 a6 blank reserved 01 a7 blank reserved 00 a8 blank reserved 00 a9 blank reserved 01 aa blank reserved 00 ab blank reserved 00 ac to ef blank lvpecl outputs f0 out0 blank out0 invert out0 lvpecl differential voltage out0 power - down 08 f1 out2 blank out1 invert out1 lvpecl differential voltage out1 power - down 0a f2 out2 blank out2 invert out2 lvpecl differential voltage out2 power - down 08 f3 out3 blank out3 invert out3 lvpecl differential voltag e out3 power - down 0a f4 out4 blank out4 invert out4 lvpecl differential voltage out4 power - down 08 f5 out5 blank out5 invert out5 lvpecl differential voltage out5 power - down 0a f6 - 13 f blank lvds/cmos outputs 140 out6 out6 cmos output polarity out6 l vds/cmos output polarity out6 cmos b out6 select lvds/cmos out6 lvds output current out6 power - down 42 141 out7 out7 cmos output polarity out7 lvds/cmos output polarity out7 cmos b out7 select lvds/cmos out7 lvds output current out7 power - down 43 142 out8 out8 cmos output polarity out8 lvds/cmos output polarity out8 cmos b out8 select lvds/cmos out8 lvds output current out8 power - down 42 143 out6 out9 cmos output polarity out9 lvds/cmos output polarity out9 cmos b out9 select lvds/cmos out9 lvds o utput current out9 power - down 43 144 - 1 8f blank lvpecl channel dividers 190 divider 0 (pecl) divider 0 low cycles divider 0 high cycles 00 191 divider 0 bypass divider 0 no sync divider 0 force high divider 0 start high divider 0 phase offset 80 192 blank reserved reserved 00 193 divider 1 (pecl) divider 1 low cycles divider 1 high cycles bb 194 divider 1 bypass divider 1 no sync divider 1 force high divider 1 start high divider 1 phase offset 00 195 blank reserved reserved 00 196 divider 2 ( pecl) divider 2 low cycles divider 2 high cycles 00 197 divider 2 bypass divider 2 no sync divider 2 force high divider 2 start high divider 2 phase offset 00 198 blank reserved reserved 00
AK8186B draft - e - 02 sep - 2012 - 45 - addr (hex) parameter bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value lvds/cmos channel dividers 199 divider 3 (lvds/cmo s) low cycles divider 3.1 high cycle divider 3.1 22 19a phase offset divider 3.2 phase offset divider 3.1 00 19b low cycles divider 3.2 high cycles divider 3.2 11 19c reser ved bypass divider3.2 bypass divider 3.1 divider 3 no sync divider 3 force high start high divider 3.2 start high divider 3.1 00 19d blank reserved reserved 00 19e divider 4 (lvds/cmo s) low cycles divider 4.1 high cycle divider 4.1 22 19f phase offset divider 4.2 phase offset divider 4.1 00 1a0 low cycles divider 4.2 high cycles divider 4.2 11 1a1 reserved bypass divider4.2 bypass divider 4.1 divider 4 no sync divider 4 force high start high divider 4.2 start high divider 4.1 00 1a2 blank reserve d reserved 00 1a 3 reserved 1a4 to 1df blank vco divider and clk input 1e0 vco divider blank reserved vco divider 02 1e1 input clks reserved power - down clock input section power - down vco clock interface power - down vco & clk select vco or clk bypass v co divider 00 1e2 to 22a blank system 230 power down and sync. reserved power - down sync power - down distribution soft sync 00 231 blank reserved 00 update all registers 232 update all registers blank update all registers 00
AK8186B sep - 2012 draft - e - 02 - 46 - r egister map functio n descriptions serial port configuration register address (hex) bit(s) name description 0x0 00 7 sdo active selects unidirectional or bidirectional data transfer mode. 0: bidirectional mode: (default) sdio pin used for write and read; sdo set high impeda nce. 1: unidirectional mode: sdo pin used for read; sdio pin used for write. 6 lsb first msb or lsb data orientation 0: data - oriented msb first: addressing decrements. (default) 1: data - oriented lsb first: addressing increments. 5 soft reset s oft reset 1: soft rest (not self - clearing); res tore s default values to internal registers. must be cleared to 0 to complete operation. 4 long instruction should be always 1 : 16bit instruction(long). 3:0 mirror[7:4] bit[3:0] should be always m irror [7:4] so that it does not matter whether the part is in msb or lsb first mode( see register 0x00[6]). user should set bits as follows. [0]=[7] [1]=[6] [2]=[5] [3]=[4] 0x0 0 3 7 :0 part id part id of the AK8186B. (read only) AK8186B : 0x43 0x0 04 0 rea d back a c tive reg. select register bank used for read back. 0: read back buffer registers (default) 1: read back active registers
AK8186B draft - e - 02 sep - 2012 - 47 - pll configuration register address (hex) bit(s) name description 0x0 10 7 pfd polarity sets the pfd polarity. the on - c hip vco requires positive polarity. 0 : positive ; higher control voltage produces higher frequency (default) 1 : negative; higher control voltage produces lower frequency 6:4 cp current charge pump current (with cp rset=5.1 k ). [6:5:4] icp(ma) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) 3:2 cp mode charge pump operating mode. [3:2] charge pump mode 0 0 high impedance state 0 1 force sour ce current (pump up) 1 0 force sink current(pump down) 1 1 normal operation. (default) 1:0 pll power down pll operating mode. [1:0] pll mode 0 0 normal operation. 0 1 asynchronous power - down. (default) 1 0 normal operation. 1 1 synchronous power - down. 0x0 11 7 :0 14 - bit r divider bits[7:0] (lsb) r divider lsbs, lower eight bits (default=0x01) . 0x0 12 5:0 14 - bit r divider bits[13:8] (msb) r divider msbs, upper six bits (default=0x00) . 0x0 13 5:0 6 - bit a counter a counter (pa rt of n divider) (default=0x00) . 0x0 14 7:0 13 - bit b counter bits[7:0] b counter (part of n divider). lower eight bits (default=0x03) . 0x0 15 4:0 13 - bit b counter bits[12:8] b counter (part of n divider). upper eight bits (default=0x00) . 0x0 16 7 set cp pin t o vdd/2 sets the cp pin to one - half of the vdd supply voltage. 0: cp normal operation (default) . 1: cp pin set to vdd/2. 6 rest r counters resets r counter (r divider) 0: normal (default) 1: reset r counter.
AK8186B sep - 2012 draft - e - 02 - 48 - register address (hex) bit (s) name description 0x0 16 5 reset a&b counters resets a&b counters (part of n divider) 0: normal (default) 1: reset a & b counter. 4 reset all counters resets r, a&b counters. 0: normal (default) 1: reset r, a & b counter. 3 b counter byp ass b counter bypass. this is valid only when operating the prescaler in fd mode. 0: normal mode (default) 1: b counter is set to divide - by - 1. this allows the prescaler setting to determine the divide for the n divider. 2:0 prescaler p prescaler: d m=dual modulus and fd = fixed divide. external vco/vcxo ; 1e1[1]=0 [2:1:0] mode prescaler 0 0 0 fd divide - by - 1 0 0 1 fd divide - by - 2 0 1 0 dm divide - by - 2 (2/3 mode) 0 1 1 dm divide - by - 4 (4/5 mode) 1 0 0 dm divide - by - 8 (8/9 mode) 1 0 1 dm divide - by - 16 (16/17 mode) 1 1 0 dm divide - by - 32 (32/33 mode) (default) 1 1 1 fd divide - by - 3 internal vco ; 1e1[1]=1 [2:1:0] mode prescaler 0 x x dm divide - by - 32 (32/33 mode) 1 0 0 dm divide - by - 8 (8/9 mode) 1 0 1 dm divide - by - 16 (16/17 mode) 1 1 x dm divide - by - 32 (32/33 mode) 0x0 17 7:2 status pin control select s the signal that is connected to the status pin. level or dynamic [7:6:5:4:3:2] signals signal at statu s pin 0 0 0 0 0 0 lvl ground(dc) (default) . 0 0 0 0 0 1 dyn n divider output 0 0 0 0 1 0 dyn r divider output 0 0 0 0 1 1 dyn a divider output. 0 0 0 1 0 0 dyn prescaler output. 0 0 0 1 0 1 dyn pfd up pulse 0 0 0 1 1 0 dyn pfd down pulse 0 x x x x x lvl ground(dc);for all other cases 0xxxxx not specified a bove. the selections that follow are the same as refmon. 1 0 0 0 0 0 lvl ground(dc). 1 0 0 0 0 1 dyn ref1 c lock 1 0 0 0 1 0 dyn ref2 clock (n/a differential mode) 1 0 0 0 1 1 dyn selected reference to pll 1 0 0 1 0 0 dyn unselected reference to pll 1 0 0 1 0 1 lvl status of selected reference 1 0 0 1 1 0 lvl status of unsel ected reference 1 0 0 1 1 1 lvl s ta tus ref1 frequency. (active high)
AK8186B draft - e - 02 sep - 2012 - 49 - register address (hex) bit(s) name description 0x0 1 7 7 :2 status pin control level or dynamic [7:6:5:4 :3:2] signals signal at status pin 1 0 1 0 0 0 lvl status ref2 frequency . (active high) 1 0 1 0 0 1 lvl (status ref1 freq.) and (status ref2 freq.) 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) 1 0 1 0 1 1 lvl status of vco frequency (a ctive high) 1 0 1 1 0 0 lvl selected reference (low=ref1,high=ref2) 1 0 1 1 0 1 lvl digital lock detect(dld); a ctive high 1 0 1 1 1 0 lvl holdover active(active high) 1 0 1 1 1 1 lvl ld pin comparator output (active high) . 1 1 0 0 0 0 lvl vdd (pll supply ) 1 1 0 0 0 1 dyn (ref1 clock)n 1 1 0 0 1 0 dyn (ref2 clock)n 1 1 0 0 1 1 dyn (selected reference to pll)n 1 1 0 1 0 0 dyn (unselected reference to pll)n 1 1 0 1 0 1 lvl status of selected refe rence: active low 1 1 0 1 1 0 lvl status of unselected reference: active low 1 1 0 1 1 1 lvl status of ref1 frequency(active low) 1 1 1 0 0 0 lvl status of ref2 frequency(active low) 1 1 1 0 0 1 lvl ((status ref1 freq.) and (status ref2 freq.))n 1 1 1 0 1 0 lvl ((dld) and (status of selected reference) and (status of vco))n 1 1 1 0 1 1 lvl status of vco frequency (active low) 1 1 1 1 0 0 lvl selected reference (low=ref2,high=ref1) . 1 1 1 1 0 1 lvl digital lock detect(dld): active low 1 1 1 1 1 0 lvl holdover active(active low) 1 1 1 1 1 1 lvl ld pin comparator output(active low) 0x0 18 6:5 lock detect counter [6:5] pfd cycles determine lock 0 0 5 (default) 0 1 16 1 0 64 1 1 255 4 digital lock detect window digital lock detect window size lock unlock 0 : high range 7.5ns 15ns (default) 1 : l ow range 3.5ns 7ns
AK8186B sep - 2012 draft - e - 02 - 50 - register address (hex) bit(s) name description 0x0 18 3 disable dld digital lock detect operation 0: normal lock detect operation (default) 1: disable lock detect 2:1 vco cal divider vco calibration divider. divider used to generate the vco calibration clock from the pll reference clock. [2:1] vco calibration clock divider 0 0 2 0 1 4 1 0 8 1 1 16 (default) 0 vco cal now bit used to initiate the vco calibration. this bit must be toggled from 0 to 1 in the active registers. the sequence to initiate a calibration is: program to 0, followed by an update bit(register 0x232[0]),; then programmed to 1, followed by another update bit(register 0x232[0]). this sequence gives complete control over when the vco calibration occurs relative to the programming of other registers that can impact the calibration. 0x0 1 9 7: 6 r,a,b counters sync pin reset [7:6] action 0 0 do nothing on sync (default) 0 1 asynchronous reset 1 0 synchronous reset 1 1 do nothing on sync 0x0 1 a 6 reference f requency monitor threshold sets the reference (ref1/ref2) frequency monitor s detection th reshold frequency. this does not affect the vco frequency monitor s detection threshold. see table 16 : ref1, ref2 and vco frequency status monitor parameter . 0: frequency valid i f frequency is above the higher frequency threshold (default) . 1: frequency valid if frequency is above the lower frequency threshold.
AK8186B draft - e - 02 sep - 2012 - 51 - register address (hex) bit(s) name description 0x0 1 a 5:0 ld pin control select s the signal that is connected to the ld pin . [5:4:3:2:1:0] signals signal at ld pin 0 0 0 0 0 0 lvl dld ( high=lock, low=unlock) (default) 0 0 0 0 0 1 dyn p - channel, open - drain lock detect(analog ld) 0 0 0 0 1 0 dyn n - channel, open - drain lock detect(analog ld) 0 0 0 0 1 1 hiz high - z ld pin. 0 0 0 1 0 0 cur current source ld(110ua when dld is true) . 0 x x x x x lvl ground(dc);for all other cases 0xxxxx not specified a bove. the selections that follow are the s ame as refm on except 101111 and 111111 . 1 0 0 0 0 0 lvl ground(dc). 1 0 0 0 0 1 dyn ref1 clock 1 0 0 0 1 0 dyn ref2 clock (n/a differential mode) 1 0 0 0 1 1 dyn selected reference to pll 1 0 0 1 0 0 dyn unselected reference to pll 1 0 0 1 0 1 lvl status of selected reference 1 0 0 1 1 0 lvl status of unselected reference 1 0 0 1 1 1 lvl sta tus ref1 frequency. (active high) 1 0 1 0 0 0 lvl status ref2 frequency. (active high) 1 0 1 0 0 1 lvl (sta tus ref1 freq.) and (status ref2 freq.) 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) 1 0 1 0 1 1 lvl status of vco frequency (active high) 1 0 1 1 0 0 lvl selected reference (low=ref1,high=ref2) 1 0 1 1 0 1 lvl digital lock detect(dld): active high 1 0 1 1 1 0 lvl holdover active(active high) 1 0 1 1 1 1 lvl n/a do not use . 1 1 0 0 0 0 lvl vdd (pll supply) 1 1 0 0 0 1 dyn (ref1 clock)n 1 1 0 0 1 0 dyn (ref 2 clock)n 1 1 0 0 1 1 dyn (selected reference to pll)n 1 1 0 1 0 0 dyn (unselected reference to pll)n 1 1 0 1 0 1 lvl status of selected reference: active low 1 1 0 1 1 0 lvl status of unselected reference: active low 1 1 0 1 1 1 lvl status of ref1 frequency(active low) 1 1 1 0 0 0 lvl status of ref2 frequency(active low) 1 1 1 0 0 1 lvl ((status ref1 freq.) and (status ref2 freq.))n 1 1 1 0 1 0 lvl ((dld) and (status of selected reference) and (status of vco))n 1 1 1 0 1 1 lvl status of vco frequency (a ctive low) 1 1 1 1 0 0 lvl selected reference (low=ref2,high=ref1). 1 1 1 1 0 1 lvl di gital lock detect(dld): active l ow 1 1 1 1 1 0 lvl holdover active(active low) 1 1 1 1 1 1 lvl n/a do not use.
AK8186B sep - 2012 draft - e - 02 - 52 - register address (hex) bit(s) name description 0x0 1b 7 vco frequency monitor enable or disable vco frequency monitor. 0: disable vco frequency monitor (default). 1: enable vco frequency monitor. 6 ref2(refin n) frequency monitor enable or disable ref2 frequency monitor. 0: disable ref2 frequency monitor (default). 1: enable ref2 frequency monitor. 5 ref1(refin) frequency monitor enable or disable ref1(refin) frequency monitor. 0: disable ref1(refin) frequ ency monitor (default). 1: enable ref1(refin) frequency monitor. 4:0 refmon pin control [4:3:2:1:0] signals signal at refmon pin 0 0 0 0 0 lvl ground(dc) (default). 0 0 0 0 1 dyn ref1 clock 0 0 0 1 0 dyn ref2 clock (n/a differ ential mode) 0 0 0 1 1 dyn selected reference to pll 0 0 1 0 0 dyn unselected reference to pll 0 0 1 0 1 lvl status of selected reference 0 0 1 1 0 lvl status of unselected reference 0 0 1 1 1 lvl status ref1 frequenc y.(active high) 0 1 0 0 0 lvl status ref2 frequency.(active high) 0 1 0 0 1 lvl (status ref1 freq.) and (status ref2 freq.) 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of vco) 0 1 0 1 1 lvl status of vco frequency (active high) 0 1 1 0 0 lvl selected reference (low=ref1,high=ref2) 0 1 1 0 1 lvl digital lock detect(dld): active high 0 1 1 1 0 lvl holdover active(active high) 0 1 1 1 1 lvl ld pin comparator output(active hi gh) 1 0 0 0 0 lvl vdd (pll supply) 1 0 0 0 1 dyn (ref1 clock)n 1 0 0 1 0 dyn (ref2 clock)n 1 0 0 1 1 dyn (selected reference to pll)n 1 0 1 0 0 dyn (unselected reference to pll)n 1 0 1 0 1 lvl status of selected reference: active low 1 0 1 1 0 lvl status of unselected reference: active low 1 0 1 1 1 lvl status of ref1 frequency(active low) 1 1 0 0 0 lvl status of ref2 frequency(active low) 1 1 0 0 1 lvl ((status ref1 freq.) and (st atus ref2 freq.))n 1 1 0 1 0 lvl ((dld) and (status of selected reference) 1 1 0 1 1 lvl status of vco frequency (active low) 1 1 1 0 0 lvl selected reference (low=ref2,high=ref1). 1 1 1 0 1 lvl digital lock detect(dld): act ive low 1 1 1 1 0 lvl holdover active(active low) 1 1 1 1 1 lvl ld pin comparator output(active low)
AK8186B draft - e - 02 sep - 2012 - 53 - register address (hex) bit(s) name description 0x0 1c 6 select ref2 if register 0x1c[5]=0, select reference for pll. 0: select ref1 (d efault) 1: select ref2 5 use ref_sel pin if register 0x1c[4]=0, set method of pll reference selection. 0: use register 0x1c[6] (default). 1: use ref_sel pin. 4 automatic reference switchover automatic or manual reference selection switchover. si ngle - ended reference mode must be selected by register 0x1c[0]=0. 0: manual reference switchover (default). 1: automatic reference switchover. 3 stay on ref2 stays on ref2 after switchover 0: return to ref1 automatically when ref1 status good aga in (default). 1: stay on ref2 after switchover. do not automatically return to ref1 . 2 ref2 power on when automatic reference switchover is disabled, this bit returns the ref2 power on. 0: ref2 power off (default). 1: ref2 power on. 1 ref1 pow er on when automatic reference switchover is disabled, this bit returns the ref1 power on. 0: ref1 power off (default). 1: ref1 power on. 0 differential reference selects the pll reference mode, differential or single - ended. single - ended must be s elected for the automatic switchover or ref1 and ref2 to work. 0: single - ended reference mode (default). 1: differential reference mode.
AK8186B sep - 2012 draft - e - 02 - 54 - register address (hex) bit(s) name description 0x0 1d 4 pll status register disable disable the pll status register read - back. 0: enable (default) 1: disable 3 ld pin comparator enable enable the ld pin voltage comparator, this function is used with the lp pin current source lock detect mode. when in the automatic holdover mode, this enables the use of the vo ltage on the ld pin to determine if the pll was previously in a locked state. otherwise, this can be used with the refmon and status pins to monitor the voltage on this pin. 0: disable (default) 1: enable 2 holdover enable a lo n g with[0] enables the h oldover function. 0: holdover disabled (default) 1: holdover enabled 1 manual holdover control enable the manual hold control through the sync pin. (this disables the automatic holdover mode.) 0: automatic holdover mode - holdover controlled by au tomatic holdover circuit. (default) 1: manual holdover mode - holdover controlled by sync pin. 0 holdover enable analog with[2] enables the holdover function. 0: holdover disabled (default) 1: holdover enabled
AK8186B draft - e - 02 sep - 2012 - 55 - register address (hex) bit(s) name description 0x0 1f 6 vco cal finished read - only register : status of the vco calibration. 0: vco calibration not finished 1: vco calibration finished 5 holdover active read - only register : indicates if the part is i n the holdover state( see fig.1 9 ). t his is not same as holdover enable. 0: not in holdover. 1: holdover state active. 4 ref2 selected read - only register : indicates which pll reference is selected as the input to pll. 0: ref1 selected (or differential reference if in differential mode .) 1: ref2 selected. 3 vco frequency > threshold read - only register : indicates if the vco frequency is greater than the threshold (see table 1 6 , ref1, ref2, and vco frequency status monitor.). 0: vco frequency is less than threshold frequency. 1: vco frequency greater the threshold frequency. 2 ref2 frequency > threshold read - only register : indicates if the frequency ref2 is greater than the threshold frequency set by register 0x1a[6]. 0: ref2 frequency is less than threshold frequency. 1: re f2 frequency greater the threshold frequency. 1 ref1 frequency > threshold read - only register : indicates if the frequency ref1 is greater than the threshold frequency set by register 0x1a[6]. 0: ref1 frequency is less than threshold frequency. 1: ref 1 frequency greater the threshold frequency. 0 digital lock detect read - only register: digital lock detect 0: pll is not locked. 1: pll is locked.
AK8186B sep - 2012 draft - e - 02 - 56 - lvpecl outputs register address (hex) bit(s) name description 0x0 f0 4 output invert selects the output polarity. 0: non - inverting (default) 1: inverting 3:2 out0 lvpecl differential voltage sets the lvpecl output differential voltage(vod) [3:2] vod(mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 1:0 out0 power - down lvpecl power - down modes. [1:0] out mode 0 0 on normal operation (default) 0 1 off partial power - down (outputs hi - z) . 1 0 off partial power - down (outputs hi - z) . 1 1 off power - down (outputs hi - z) 0x0 f1 4 output invert selects output polarity. 0: non - inverting (default) 1: inverting 3:2 out1 lvpecl differential voltage sets the lvpecl output differential voltage(vod) [3:2] vod(mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 1:0 out1 power - down lvpecl power - down modes. [1 :0] out mode 0 0 on normal operation 0 1 off partial power - down (outputs hi - z) . 1 0 off partial power - down (outputs hi - z) . (default) 1 1 off power - down (outputs hi - z). 0x0 f2 4 output invert selects output polarity. 0: non - inverting (def ault) 1: inverting 3:2 out2 lvpecl differential voltage sets the lvpecl output differential voltage(vod) [3:2] vod(mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 1:0 out2 power - down lvpecl power - down modes. [1:0] out mode 0 0 on normal operation (default) 0 1 off partial power - down (outputs hi - z) . 1 0 off partial power - down (outputs hi - z) . 1 1 off power - down (outputs hi - z).
AK8186B draft - e - 02 sep - 2012 - 57 - register address (hex) bit(s) name description 0x0 f3 4 output invert selects output p olarity. 0: non - inverting (default) 1: inverting 3:2 out3 lvpecl differential voltage sets the lvpecl output differential voltage(vod) [3:2] vod(mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 1:0 out3 power - down lvpecl power - down m odes. [1:0] out mode 0 0 on normal operation 0 1 off partial power - down (outputs hi - z) . 1 0 off partial power - down (outputs hi - z) . (default) 1 1 off power - down (outputs hi - z). 0x0 f4 4 output invert selects output polarity. 0: non - inver ting (default) 1: inverting 3:2 out4 lvpecl differential voltage sets the lvpecl output differential voltage(vod) [3:2] vod(mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 1:0 out4 power - down lvpecl power - down modes. [1:0] out mo de 0 0 on normal operation (default) 0 1 off partial power - down (outputs hi - z) . 1 0 off partial power - down (outputs hi - z) . 1 1 off power - down (outputs hi - z). 0x0 f5 4 output invert selects output polarity. 0: non - inverting (default) 1: inv erting 3:2 out5 lvpecl differential voltage sets the lvpecl output differential voltage(vod) [3:2] vod(mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 1:0 out5 power - down lvpecl power - down modes. [1:0] out mode 0 0 on normal operation 0 1 off partial power - down (outputs hi - z) . 1 0 off partial power - down (outputs hi - z) . (default) 1 1 off power - down (outputs hi - z).
AK8186B sep - 2012 draft - e - 02 - 58 - lvds/cmos outputs register address (hex) bit(s) name description 0x 140 7:5 out6 output polarity in cmos mode,[7:5] select the output polarity of each cmos output. in lvds mode, only [5] determines ldvs polarity. [7:6:5] out6(cmos) out6n(cmos) out6(lvds) 0 0 0 non - inverting. inverting. non - inverting. 0 1 0 non - inve rting. non - inverting. non - inverting (default) 1 0 0 inverting. inverting. non - inverting 1 1 0 inverting. non - inverting. non - inverting 0 0 1 inverting. non - inverting. inverting 0 1 1 in verting. inverting. inverting 1 0 1 non - inverting. non - inverting. inverting 1 1 1 non - inverting. inverting. inverting 4 out6 cmos b in cmos mode, turn on/off the out6n output. there is no effect in ldvs mode . 0: turn off the out6n output. (default) 1: turn on the out6n output.. 3 out6 select lvds/cmos selects lvds or cmos logic levels. 0: lvds. (default) 1: cmos. 2:1 out6 lvds output current sets output current level in lvds mode. this has no effect cmos mode, [2:1] current (ma) recommend termination ( ) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7.0 50 0 out6 power - down power - down output(lvds/cmos). 0: power on. 1: power off. (default ) lvds: outputs hi - z cmos: outputs low 0x 141 7:5 out 7 output polarity in cmos mode,[7:5] select the output polarity of each cmos output. in lvds mode, only [5] determines ldvs polarity. [7:6:5] out7(cmos) out7n(cmos) out7(lvds) 0 0 0 non - inverting. inverting. non - inverting. 0 1 0 non - inverting. non - inverting. non - inverting (default) 1 0 0 inverting. inverting. non - inverting 1 1 0 inverting. non - inverting. non - inverting 0 0 1 inverting. non - inverting. inver ting 0 1 1 inverting. inverting. inverting 1 0 1 non - inverting. non - inverting. inverting 1 1 1 non - inverting. inverting. inverting 4 out7 cmos b in cmos mode, turn on/off the out7n output. there is no e ffect in ldvs mode. 0: turn off the out7n output. (default) 1: turn on the out7n output.. 3 out7 select lvds/cmos selects lvds or cmos logic levels. 0: lvds. (default) 1: cmos. 2:1 out7 lvds output current sets output current level in lvds mode. this has no effect cmos mode, [2:1] current (ma) recommend termination ( ) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7.0 50
AK8186B draft - e - 02 sep - 2012 - 59 - register address (hex) bit(s) name description 141 0 out7 powe r - down power - down output(lvds/cmos). 0: power on. 1: power off. ( default ) lvds: outputs hi - z cmos: outputs low 0x 142 7:5 out8 output polarity in cmos mode,[7:5] select the output polarity of each cmos output. in lvds mode, only [5] determines ldvs pola rity. [7:6:5] out8(cmos) out8n(cmos) out8(lvds) 0 0 0 non - inverting. inverting. non - inverting. 0 1 0 non - inverting. non - inverting. non - inverting (default) 1 0 0 inverting. inverting. non - in verting 1 1 0 inverting. non - inverting. non - inverting 0 0 1 inverting. non - inverting. inverting 0 1 1 inverting. inverting. inverting 1 0 1 non - inverting. non - inverting. inverting 1 1 1 non - inverting. inverting. inverting 4 out8 cmos b in cmos mode, turn on/off the out8n output. there is no effect in ldvs mode. 0: turn off the out8n output. (default) 1: turn on the out8n output.. 3 out8 select lvds/cmos selects lv ds or cmos logic levels. 0: lvds. 1: cmos. 2:1 out8 lvds output current sets output current level in lvds mode. this has no effect cmos mode, [2:1] current (ma) recommend termination ( ) 0 0 1.75 100 0 1 3.5 100 (default ) 1 0 5.25 50 1 1 7.0 50 0 out8 power - down power - down output(lvds/cmos). 0: power on. 1: power off. ( default ) lvds: outputs hi - z cmos: outputs low 0x 143 7:5 out9 output polarity in cmos mode,[7:5] select the output polarity of each cmos output. in lvds mode, only [5] determines ldvs polarity. [7:6:5] out9(cmos) out9n(cmos) out9(lvds) 0 0 0 non - inverting. inverting. non - inverting. 0 1 0 non - inverting. non - inverting. non - inverting ( default) 1 0 0 inverting. inverting. non - inverting 1 1 0 inverting. non - inverting. non - inverting 0 0 1 inverting. non - inverting. inverting 0 1 1 inverting. inverting. inverting 1 0 1 non - inverting. non - inverting. inverting 1 1 1 non - inverting. inverting. inverting 4 out9 cmos b in cmos mode, turn on/off the out9n output. there is no effect in ldvs mode. 0: turn off the out9n output. (default) 1: turn on the out9n output.. 3 out9 select lvds/cmos selects lvds or cmos logic levels. 0: lvds. (default) 1: cmos.
AK8186B sep - 2012 draft - e - 02 - 60 - lvpecl channe l dividers register address (hex) bit(s) name description 0x 143 2:1 out9 lvds output current sets output current level in lvds mode. this ha s no effect cmos mode, [2:1] current (ma) recommend termination ( ) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7.0 50 0 out9 power - down power - down output(lvds/cmos). 0: power on. 1: power off. ( default ) lvds: outputs hi - z cmos: outputs low register address (hex) bit(s) name description 0x 190 7:4 divider 0 low cycles m number of low clock cycles (m) and high clock cycles (n) of the divider input define a frequency division, dx, of the divider 0. dx = m+n+2. note) the m and n doe s not affect the duty of lvpecl output. t h e dcc(duty cycle correction) always works. 3:0 divider 0 h i gh cycles n 0x 191 7 divider 0 bypass bypasses and power - down the divider; route input to divider output. 0: use divider. 1: bypass divider. (default) 6 divider 0 nosync nosync. 0: obey chip - level sync signal. (default) 1: ignore chip - level sync signal. 5 divider 0 force high forces divider output to high. this requires that nosync also be set. 0: divider output force to low. (default) 1: divider o utput force to high. 4 divider 0 start high selects clock output to start high or start low. 0: start low. (default) 1: start high. 3:0 divider 0 phase offset phase offset. (default=0x0) 0x 193 7:4 divider 1 low cycles m number of low clock cycles (m) and high clock cycles (n) of the divider input define a frequency division, dx, of the divider 1. dx = m+n+2. note) the m and n does not affect the duty of lvpecl output. t h e dcc(duty cycle correction) always works. 3:0 divider 1 h i gh cycles n 0x 194 7 divider 1 bypass bypasses and power - down the divider; route input to divider output. 0: use divider. (default) 1: bypass divider. 6 divider 1 nosync nosync. 0: obey chip - level sync signal. (default) 1: ignore chip - level sync signal. 5 divider 1 fo rce high forces divider output to high. this requires that nosync also be set. 0: divider output force to low. (default) 1: divider output force to high.
AK8186B draft - e - 02 sep - 2012 - 61 - register address (hex) bit(s) name description 0x 194 4 divider 1 start high selects clock output to start high or start low. 0: start low. (default) 1: start high. 3:0 divider 1 phase offset phase offset. (default=0x0) 0x 196 7:4 divider 2 low cycles m number of low clock cycles (m) and high clock cycles (n) of the divider input define a frequency division, dx, of the divider 2. dx = m+n+2. note) the m and n does not affect the duty of lvpecl output. t h e dcc(duty cycle correction) always works. 3:0 divider 2 h i gh cycles n 0x 197 7 divider 2 bypass bypasses and power - down the divider; route inpu t to divider output. 0: use divider. (default) 1: bypass divider. 6 divider 2 nosync nosync. 0: obey chip - level sync signal. (default) 1: ignore chip - level sync signal. 5 divider 2 force high forces divider output to high. this requires that nosync a lso be set. 0: divider output force to low. (default) 1: divider output force to high. 4 divider 2 start high selects clock output to start high or start low. 0: start low. (default) 1: start high. 3:0 divider 2 phase offset phase offset. (default=0x0)
AK8186B sep - 2012 draft - e - 02 - 62 - lvds/cmos channel dividers register address (hex) bit(s) name description 0x 199 7:4 divider 3.1 low cycles m number of low clock cycles (m) and high clock cycles (n) of the divider input define a frequency division, dx, of the divider 3.1. dx = m+n+ 2. note) the m and n does not affect the duty of lvds/cmos output. t h e dcc(duty cycle correction) always works. 3:0 divider 3.1 h i gh cycles n 0x 19a 7:4 divider 3.2 phase offset refer to lvds/cmos channel divider function description. 3:0 divider 3.1 phase offset refer to lvds/cmos channel divider function description. 0x 19b 7:4 divider 3.2 low cycles number of low clock cycles (m) and high clock cycles (n) of the divider input define a frequency division, dx, of the divider 3.2. dx = m+n+2. note) th e m and n does not affect the duty of lvds/cmos output. t h e dcc(duty cycle correction) always works. 3:0 divider 3.2 h i gh cycles 0x 19c 5 divider 3.2 bypass bypasses (and power - down)3.2 divider logic, route input to 3.2 output. 0: do not bypass. (defaul t) 1: bypass. 4 divider 3.1 bypass bypasses (and power - down)3.1 divider logic, route input to 3.2 output. 0: do not bypass. (default) 1: bypass. 3 divider 3 nosync nosync. 0: obey chip - level sync signal. (default) 1: ignore chip - level sync signal. 2 divider 3 force h i gh forces divider 3 output to high. requires that nosync also be set. 0: force low. (default) 1: force high. 1 divider 3.2 start high divider3.2 start high or start low. 0: start low. (default) 1: start high. 0 divider 3.1 start hig h divider3.1 strat high or start low. 0: start low. (default) 1: start high.
AK8186B draft - e - 02 sep - 2012 - 63 - register address (hex) bit(s) name description 0x 19e 7:4 divider 4.1 low cycles m number of low clock cycles (m) and high clock cycles (n) of the divider input define a freq uency division, dx, of the divider 4.1. dx = m+n+2. note) the m and n does not affect the duty of lvds/cmos output. t h e dcc(duty cycle correction) always works. 3:0 divider 4.1 h i gh cycles n 0x 19f 7:4 divider 4.2 phase offset refer to lvds/cmos channe l divider function description. 3:0 divider 4.1 phase offset refer to lvds/cmos channel divider function description. 0x 1a0 7:4 divider 4.2 low cycles number of low clock cycles (m) and high clock cycles (n) of the divider input define a frequency divis ion, dx, of the divider 4.2. dx = m+n+2. note) the m and n does not affect the duty of lvds/cmos output. t h e dcc(duty cycle correction) always works. 3:0 divider 4.2 h i gh cycles 0x 1a1 5 divider 4.2 bypass bypasses (and power - down)4.2 divider logic, ro ute input to 4.2 output. 0: do not bypass. (default) 1: bypass. 4 divider 4.1 bypass bypasses (and power - down)4.1 divider logic, route input to 4.2 output. 0: do not bypass. (default) 1: bypass. 3 divider 4 nosync nosync. 0: obey chip - level sync sign al. (default) 1: ignore chip - level sync signal. 2 divider 4 force h i gh forces divider 4 output to high. requires that nosync also be set. 0: force low. (default) 1: force high. 1 divider 4.2 start high divider4.2 start high or start low. 0: start low. (default) 1: start high. 0 divider 4.1 start high divider4.1 strat high or start low. 0: start low. (default) 1: start high.
AK8186B sep - 2012 draft - e - 02 - 64 - vco divider and clk input register address (hex) bit(s) name description 0x 1e0 2:0 vco divider [2:1:0] divide 0 0 0 2 0 0 1 3 0 1 0 4 (default) 0 1 1 5 1 0 0 6 1 0 1 output static 1 1 0 output static 1 1 1 output static 0x 1e1 4 power - down clock input section powers down the clock input section (including clk buffer, vco dividers and clk tree). 0 : normal operation (default). 1 : power - down. 3 power - down vco clock interface powers down the interface block between vco and clock distribution. 0 : normal operation (default). 1 : power - down. 2 power - down vco and clk powers down both vco and clk input. 0 : normal operation (default). 1 : power - down. 1 select vco or clk powers down the clock input section (including clk buffer, vco dividers and clk tree). 0 : selects external clk as input to vco divider (def ault). 1 : selects vco as input to vco divider; cannot bypass vco divider when this is selected. 0 bypass vco divider bypasses or use s the vco divider. 0 : uses vco divider (default). 1 : bypasses vco divider; cannnot select vco as input when this is selected.
AK8186B draft - e - 02 sep - 2012 - 65 - system update all registers register address (hex) bit(s) name description 0x 230 2 power - down sync powers down the sync function. 0: normal operation of sync function (default) . 1: power - dow n sync circuitry. 1 power down distribution reference powers down the output buffers. 0 : normal operation (default). 1 : power down the output buffers. buffers output as follows in power down. lvpecl: hi - z (same state with 0xfn[1:0]=01 or 10 b, n=0 to 5) lvds: hi - z cmos: l ow 0 soft sync the soft sync works the same as the sync pin. e xpect that the polarity of the bit is reversed. that is, a high level forces selected channels into a predetermined static state, and 1 - to - 0 transition triggers a sync. 0: same as sync high (default) . 1: same as sync low. register address (hex) bit(s) name description 0x 232 0 update all registers this bit must be set to 1 to transfer the contents of the buffer registers int o the active registers. this happens on the next sclk rising edge. this bit is self - cleaning; that is, it does not have to be set back to 0. 1 : (self - cleaning); update all active registers to the contents of the buffer registers.
AK8186B sep - 2012 draft - e - 02 - 66 - p ackage i nformation m echanical data marking a: #1 pin index b: part number c: date code a b c c 0 . 6 0 m a x 0 . 8 5 + 0 . 1 5 - 0 . 0 5 +0.07 -0.05 0 . 2 0 0 . 0 2 + 0 . 0 3 - 0 . 0 2 9.00 8.75 9 . 0 0 8 . 7 5 0.25 +0.05 -0.07 6.15 6 . 1 5 m 0.10 ab a b 1 1 64 49 17 33 17 33 49 64 16 16 32 32 48 48 s 0.40.10 0.50 s 0.08
AK8186B draft - e - 02 sep - 2012 - 67 - rohs complian ce all integrated circuits form asahi kasei m icrodevices corporation (akm) assembled in lead - free packages* are fully compliant with rohs. (*) rohs compliant products from akm are identified with pb free letter indication on product label posted on the anti - shield bag and boxes.
AK8186B sep - 2012 draft - e - 02 - 68 - revision history 31/august/2012 draft - e00 to e01 p.3 adds table of contents. p. 8 change to on chip vco . p. 9 change to input capaci tance. p.25 change to prescaler division in fd and dm mode. p.27 change to p - channel open drain in figure17. p.49 change to lock detect counter. 28/september/2012 draft - e01 to e02 p. 12 - 15 change to table 8 ,9, 10 ,12 and 13 .
AK8186B draft - e - 02 sep - 2012 - 69 - im portant notice ? these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized di stributors as to current status of the products. ? descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semico nductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or thi rd parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or de vices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intende d nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representativ e director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless fr om any and all claims arising from the use of said product in the absence of such notification.

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